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Merge tag 'v5.2-rc1' into asoc-5.3

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Linux 5.2-rc1
This commit is contained in:
Mark Brown
2019-05-20 11:53:50 +01:00
parent bfa8130f50 a188339ca5
commit 1c7c3237c0
11433 changed files with 503760 additions and 323397 deletions
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30
include/dt-bindings/clock/axg-audio-clkc.h
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@@ -7,26 +7,6 @@
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
#define __AXG_AUDIO_CLKC_BINDINGS_H
#define AUD_CLKID_SLV_SCLK0 9
#define AUD_CLKID_SLV_SCLK1 10
#define AUD_CLKID_SLV_SCLK2 11
#define AUD_CLKID_SLV_SCLK3 12
#define AUD_CLKID_SLV_SCLK4 13
#define AUD_CLKID_SLV_SCLK5 14
#define AUD_CLKID_SLV_SCLK6 15
#define AUD_CLKID_SLV_SCLK7 16
#define AUD_CLKID_SLV_SCLK8 17
#define AUD_CLKID_SLV_SCLK9 18
#define AUD_CLKID_SLV_LRCLK0 19
#define AUD_CLKID_SLV_LRCLK1 20
#define AUD_CLKID_SLV_LRCLK2 21
#define AUD_CLKID_SLV_LRCLK3 22
#define AUD_CLKID_SLV_LRCLK4 23
#define AUD_CLKID_SLV_LRCLK5 24
#define AUD_CLKID_SLV_LRCLK6 25
#define AUD_CLKID_SLV_LRCLK7 26
#define AUD_CLKID_SLV_LRCLK8 27
#define AUD_CLKID_SLV_LRCLK9 28
#define AUD_CLKID_DDR_ARB 29
#define AUD_CLKID_PDM 30
#define AUD_CLKID_TDMIN_A 31
@@ -90,5 +70,15 @@
#define AUD_CLKID_TDMOUT_A_LRCLK 134
#define AUD_CLKID_TDMOUT_B_LRCLK 135
#define AUD_CLKID_TDMOUT_C_LRCLK 136
#define AUD_CLKID_SPDIFOUT_B 151
#define AUD_CLKID_SPDIFOUT_B_CLK 152
#define AUD_CLKID_TDM_MCLK_PAD0 155
#define AUD_CLKID_TDM_MCLK_PAD1 156
#define AUD_CLKID_TDM_LRCLK_PAD0 157
#define AUD_CLKID_TDM_LRCLK_PAD1 158
#define AUD_CLKID_TDM_LRCLK_PAD2 159
#define AUD_CLKID_TDM_SCLK_PAD0 160
#define AUD_CLKID_TDM_SCLK_PAD1 161
#define AUD_CLKID_TDM_SCLK_PAD2 162
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */

3
include/dt-bindings/clock/exynos5410.h
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@@ -36,6 +36,7 @@
#define CLK_UART0 257
#define CLK_UART1 258
#define CLK_UART2 259
#define CLK_UART3 260
#define CLK_I2C0 261
#define CLK_I2C1 262
#define CLK_I2C2 263
@@ -44,7 +45,7 @@
#define CLK_USI1 266
#define CLK_USI2 267
#define CLK_USI3 268
#define CLK_UART3 260
#define CLK_TSADC 270
#define CLK_PWM 279
#define CLK_MCT 315
#define CLK_WDT 316

2
include/dt-bindings/clock/g12a-aoclkc.h
View File

@@ -26,7 +26,9 @@
#define CLKID_AO_M4_FCLK 13
#define CLKID_AO_M4_HCLK 14
#define CLKID_AO_CLK81 15
#define CLKID_AO_SAR_ADC_SEL 16
#define CLKID_AO_SAR_ADC_CLK 18
#define CLKID_AO_CTS_OSCIN 19
#define CLKID_AO_32K 23
#define CLKID_AO_CEC 27
#define CLKID_AO_CTS_RTC_OSCIN 28

5
include/dt-bindings/clock/g12a-clkc.h
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@@ -131,5 +131,10 @@
#define CLKID_MALI_1 174
#define CLKID_MALI 175
#define CLKID_MPLL_5OM 177
#define CLKID_CPU_CLK 187
#define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1 204
#define CLKID_VDEC_HEVC 207
#define CLKID_VDEC_HEVCF 210
#endif /* __G12A_CLKC_H */

1
include/dt-bindings/clock/imx7ulp-clock.h
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@@ -65,7 +65,6 @@
#define IMX7ULP_CLK_FLEXBUS 2
#define IMX7ULP_CLK_SEMA42_1 3
#define IMX7ULP_CLK_DMA_MUX1 4
#define IMX7ULP_CLK_SNVS 5
#define IMX7ULP_CLK_CAAM 6
#define IMX7ULP_CLK_LPTPM4 7
#define IMX7ULP_CLK_LPTPM5 8

1
include/dt-bindings/clock/jz4725b-cgu.h
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@@ -31,5 +31,6 @@
#define JZ4725B_CLK_TCU 22
#define JZ4725B_CLK_EXT512 23
#define JZ4725B_CLK_RTC 24
#define JZ4725B_CLK_UDC_PHY 25
#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */

6
include/dt-bindings/clock/meson8b-clkc.h
View File

@@ -103,10 +103,14 @@
#define CLKID_MPLL1 94
#define CLKID_MPLL2 95
#define CLKID_NAND_CLK 112
#define CLKID_ABP 124
#define CLKID_APB 124
#define CLKID_PERIPH 126
#define CLKID_AXI 128
#define CLKID_L2_DRAM 130
#define CLKID_VPU 190
#define CLKID_VDEC_1 196
#define CLKID_VDEC_HCODEC 199
#define CLKID_VDEC_2 202
#define CLKID_VDEC_HEVC 206
#endif /* __MESON8B_CLKC_H */

422
include/dt-bindings/clock/mt8183-clk.h Normal file
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@@ -0,0 +1,422 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
*/
#ifndef _DT_BINDINGS_CLK_MT8183_H
#define _DT_BINDINGS_CLK_MT8183_H
/* APMIXED */
#define CLK_APMIXED_ARMPLL_LL 0
#define CLK_APMIXED_ARMPLL_L 1
#define CLK_APMIXED_CCIPLL 2
#define CLK_APMIXED_MAINPLL 3
#define CLK_APMIXED_UNIV2PLL 4
#define CLK_APMIXED_MSDCPLL 5
#define CLK_APMIXED_MMPLL 6
#define CLK_APMIXED_MFGPLL 7
#define CLK_APMIXED_TVDPLL 8
#define CLK_APMIXED_APLL1 9
#define CLK_APMIXED_APLL2 10
#define CLK_APMIXED_SSUSB_26M 11
#define CLK_APMIXED_APPLL_26M 12
#define CLK_APMIXED_MIPIC0_26M 13
#define CLK_APMIXED_MDPLLGP_26M 14
#define CLK_APMIXED_MMSYS_26M 15
#define CLK_APMIXED_UFS_26M 16
#define CLK_APMIXED_MIPIC1_26M 17
#define CLK_APMIXED_MEMPLL_26M 18
#define CLK_APMIXED_CLKSQ_LVPLL_26M 19
#define CLK_APMIXED_MIPID0_26M 20
#define CLK_APMIXED_MIPID1_26M 21
#define CLK_APMIXED_NR_CLK 22
/* TOPCKGEN */
#define CLK_TOP_MUX_AXI 0
#define CLK_TOP_MUX_MM 1
#define CLK_TOP_MUX_CAM 2
#define CLK_TOP_MUX_MFG 3
#define CLK_TOP_MUX_CAMTG 4
#define CLK_TOP_MUX_UART 5
#define CLK_TOP_MUX_SPI 6
#define CLK_TOP_MUX_MSDC50_0_HCLK 7
#define CLK_TOP_MUX_MSDC50_0 8
#define CLK_TOP_MUX_MSDC30_1 9
#define CLK_TOP_MUX_MSDC30_2 10
#define CLK_TOP_MUX_AUDIO 11
#define CLK_TOP_MUX_AUD_INTBUS 12
#define CLK_TOP_MUX_FPWRAP_ULPOSC 13
#define CLK_TOP_MUX_SCP 14
#define CLK_TOP_MUX_ATB 15
#define CLK_TOP_MUX_SSPM 16
#define CLK_TOP_MUX_DPI0 17
#define CLK_TOP_MUX_SCAM 18
#define CLK_TOP_MUX_AUD_1 19
#define CLK_TOP_MUX_AUD_2 20
#define CLK_TOP_MUX_DISP_PWM 21
#define CLK_TOP_MUX_SSUSB_TOP_XHCI 22
#define CLK_TOP_MUX_USB_TOP 23
#define CLK_TOP_MUX_SPM 24
#define CLK_TOP_MUX_I2C 25
#define CLK_TOP_MUX_F52M_MFG 26
#define CLK_TOP_MUX_SENINF 27
#define CLK_TOP_MUX_DXCC 28
#define CLK_TOP_MUX_CAMTG2 29
#define CLK_TOP_MUX_AUD_ENG1 30
#define CLK_TOP_MUX_AUD_ENG2 31
#define CLK_TOP_MUX_FAES_UFSFDE 32
#define CLK_TOP_MUX_FUFS 33
#define CLK_TOP_MUX_IMG 34
#define CLK_TOP_MUX_DSP 35
#define CLK_TOP_MUX_DSP1 36
#define CLK_TOP_MUX_DSP2 37
#define CLK_TOP_MUX_IPU_IF 38
#define CLK_TOP_MUX_CAMTG3 39
#define CLK_TOP_MUX_CAMTG4 40
#define CLK_TOP_MUX_PMICSPI 41
#define CLK_TOP_SYSPLL_CK 42
#define CLK_TOP_SYSPLL_D2 43
#define CLK_TOP_SYSPLL_D3 44
#define CLK_TOP_SYSPLL_D5 45
#define CLK_TOP_SYSPLL_D7 46
#define CLK_TOP_SYSPLL_D2_D2 47
#define CLK_TOP_SYSPLL_D2_D4 48
#define CLK_TOP_SYSPLL_D2_D8 49
#define CLK_TOP_SYSPLL_D2_D16 50
#define CLK_TOP_SYSPLL_D3_D2 51
#define CLK_TOP_SYSPLL_D3_D4 52
#define CLK_TOP_SYSPLL_D3_D8 53
#define CLK_TOP_SYSPLL_D5_D2 54
#define CLK_TOP_SYSPLL_D5_D4 55
#define CLK_TOP_SYSPLL_D7_D2 56
#define CLK_TOP_SYSPLL_D7_D4 57
#define CLK_TOP_UNIVPLL_CK 58
#define CLK_TOP_UNIVPLL_D2 59
#define CLK_TOP_UNIVPLL_D3 60
#define CLK_TOP_UNIVPLL_D5 61
#define CLK_TOP_UNIVPLL_D7 62
#define CLK_TOP_UNIVPLL_D2_D2 63
#define CLK_TOP_UNIVPLL_D2_D4 64
#define CLK_TOP_UNIVPLL_D2_D8 65
#define CLK_TOP_UNIVPLL_D3_D2 66
#define CLK_TOP_UNIVPLL_D3_D4 67
#define CLK_TOP_UNIVPLL_D3_D8 68
#define CLK_TOP_UNIVPLL_D5_D2 69
#define CLK_TOP_UNIVPLL_D5_D4 70
#define CLK_TOP_UNIVPLL_D5_D8 71
#define CLK_TOP_APLL1_CK 72
#define CLK_TOP_APLL1_D2 73
#define CLK_TOP_APLL1_D4 74
#define CLK_TOP_APLL1_D8 75
#define CLK_TOP_APLL2_CK 76
#define CLK_TOP_APLL2_D2 77
#define CLK_TOP_APLL2_D4 78
#define CLK_TOP_APLL2_D8 79
#define CLK_TOP_TVDPLL_CK 80
#define CLK_TOP_TVDPLL_D2 81
#define CLK_TOP_TVDPLL_D4 82
#define CLK_TOP_TVDPLL_D8 83
#define CLK_TOP_TVDPLL_D16 84
#define CLK_TOP_MSDCPLL_CK 85
#define CLK_TOP_MSDCPLL_D2 86
#define CLK_TOP_MSDCPLL_D4 87
#define CLK_TOP_MSDCPLL_D8 88
#define CLK_TOP_MSDCPLL_D16 89
#define CLK_TOP_AD_OSC_CK 90
#define CLK_TOP_OSC_D2 91
#define CLK_TOP_OSC_D4 92
#define CLK_TOP_OSC_D8 93
#define CLK_TOP_OSC_D16 94
#define CLK_TOP_F26M_CK_D2 95
#define CLK_TOP_MFGPLL_CK 96
#define CLK_TOP_UNIVP_192M_CK 97
#define CLK_TOP_UNIVP_192M_D2 98
#define CLK_TOP_UNIVP_192M_D4 99
#define CLK_TOP_UNIVP_192M_D8 100
#define CLK_TOP_UNIVP_192M_D16 101
#define CLK_TOP_UNIVP_192M_D32 102
#define CLK_TOP_MMPLL_CK 103
#define CLK_TOP_MMPLL_D4 104
#define CLK_TOP_MMPLL_D4_D2 105
#define CLK_TOP_MMPLL_D4_D4 106
#define CLK_TOP_MMPLL_D5 107
#define CLK_TOP_MMPLL_D5_D2 108
#define CLK_TOP_MMPLL_D5_D4 109
#define CLK_TOP_MMPLL_D6 110
#define CLK_TOP_MMPLL_D7 111
#define CLK_TOP_CLK26M 112
#define CLK_TOP_CLK13M 113
#define CLK_TOP_ULPOSC 114
#define CLK_TOP_UNIVP_192M 115
#define CLK_TOP_MUX_APLL_I2S0 116
#define CLK_TOP_MUX_APLL_I2S1 117
#define CLK_TOP_MUX_APLL_I2S2 118
#define CLK_TOP_MUX_APLL_I2S3 119
#define CLK_TOP_MUX_APLL_I2S4 120
#define CLK_TOP_MUX_APLL_I2S5 121
#define CLK_TOP_APLL12_DIV0 122
#define CLK_TOP_APLL12_DIV1 123
#define CLK_TOP_APLL12_DIV2 124
#define CLK_TOP_APLL12_DIV3 125
#define CLK_TOP_APLL12_DIV4 126
#define CLK_TOP_APLL12_DIVB 127
#define CLK_TOP_UNIVPLL 128
#define CLK_TOP_ARMPLL_DIV_PLL1 129
#define CLK_TOP_ARMPLL_DIV_PLL2 130
#define CLK_TOP_UNIVPLL_D3_D16 131
#define CLK_TOP_NR_CLK 132
/* CAMSYS */
#define CLK_CAM_LARB6 0
#define CLK_CAM_DFP_VAD 1
#define CLK_CAM_CAM 2
#define CLK_CAM_CAMTG 3
#define CLK_CAM_SENINF 4
#define CLK_CAM_CAMSV0 5
#define CLK_CAM_CAMSV1 6
#define CLK_CAM_CAMSV2 7
#define CLK_CAM_CCU 8
#define CLK_CAM_LARB3 9
#define CLK_CAM_NR_CLK 10
/* INFRACFG_AO */
#define CLK_INFRA_PMIC_TMR 0
#define CLK_INFRA_PMIC_AP 1
#define CLK_INFRA_PMIC_MD 2
#define CLK_INFRA_PMIC_CONN 3
#define CLK_INFRA_SCPSYS 4
#define CLK_INFRA_SEJ 5
#define CLK_INFRA_APXGPT 6
#define CLK_INFRA_ICUSB 7
#define CLK_INFRA_GCE 8
#define CLK_INFRA_THERM 9
#define CLK_INFRA_I2C0 10
#define CLK_INFRA_I2C1 11
#define CLK_INFRA_I2C2 12
#define CLK_INFRA_I2C3 13
#define CLK_INFRA_PWM_HCLK 14
#define CLK_INFRA_PWM1 15
#define CLK_INFRA_PWM2 16
#define CLK_INFRA_PWM3 17
#define CLK_INFRA_PWM4 18
#define CLK_INFRA_PWM 19
#define CLK_INFRA_UART0 20
#define CLK_INFRA_UART1 21
#define CLK_INFRA_UART2 22
#define CLK_INFRA_UART3 23
#define CLK_INFRA_GCE_26M 24
#define CLK_INFRA_CQ_DMA_FPC 25
#define CLK_INFRA_BTIF 26
#define CLK_INFRA_SPI0 27
#define CLK_INFRA_MSDC0 28
#define CLK_INFRA_MSDC1 29
#define CLK_INFRA_MSDC2 30
#define CLK_INFRA_MSDC0_SCK 31
#define CLK_INFRA_DVFSRC 32
#define CLK_INFRA_GCPU 33
#define CLK_INFRA_TRNG 34
#define CLK_INFRA_AUXADC 35
#define CLK_INFRA_CPUM 36
#define CLK_INFRA_CCIF1_AP 37
#define CLK_INFRA_CCIF1_MD 38
#define CLK_INFRA_AUXADC_MD 39
#define CLK_INFRA_MSDC1_SCK 40
#define CLK_INFRA_MSDC2_SCK 41
#define CLK_INFRA_AP_DMA 42
#define CLK_INFRA_XIU 43
#define CLK_INFRA_DEVICE_APC 44
#define CLK_INFRA_CCIF_AP 45
#define CLK_INFRA_DEBUGSYS 46
#define CLK_INFRA_AUDIO 47
#define CLK_INFRA_CCIF_MD 48
#define CLK_INFRA_DXCC_SEC_CORE 49
#define CLK_INFRA_DXCC_AO 50
#define CLK_INFRA_DRAMC_F26M 51
#define CLK_INFRA_IRTX 52
#define CLK_INFRA_DISP_PWM 53
#define CLK_INFRA_CLDMA_BCLK 54
#define CLK_INFRA_AUDIO_26M_BCLK 55
#define CLK_INFRA_SPI1 56
#define CLK_INFRA_I2C4 57
#define CLK_INFRA_MODEM_TEMP_SHARE 58
#define CLK_INFRA_SPI2 59
#define CLK_INFRA_SPI3 60
#define CLK_INFRA_UNIPRO_SCK 61
#define CLK_INFRA_UNIPRO_TICK 62
#define CLK_INFRA_UFS_MP_SAP_BCLK 63
#define CLK_INFRA_MD32_BCLK 64
#define CLK_INFRA_SSPM 65
#define CLK_INFRA_UNIPRO_MBIST 66
#define CLK_INFRA_SSPM_BUS_HCLK 67
#define CLK_INFRA_I2C5 68
#define CLK_INFRA_I2C5_ARBITER 69
#define CLK_INFRA_I2C5_IMM 70
#define CLK_INFRA_I2C1_ARBITER 71
#define CLK_INFRA_I2C1_IMM 72
#define CLK_INFRA_I2C2_ARBITER 73
#define CLK_INFRA_I2C2_IMM 74
#define CLK_INFRA_SPI4 75
#define CLK_INFRA_SPI5 76
#define CLK_INFRA_CQ_DMA 77
#define CLK_INFRA_UFS 78
#define CLK_INFRA_AES_UFSFDE 79
#define CLK_INFRA_UFS_TICK 80
#define CLK_INFRA_MSDC0_SELF 81
#define CLK_INFRA_MSDC1_SELF 82
#define CLK_INFRA_MSDC2_SELF 83
#define CLK_INFRA_SSPM_26M_SELF 84
#define CLK_INFRA_SSPM_32K_SELF 85
#define CLK_INFRA_UFS_AXI 86
#define CLK_INFRA_I2C6 87
#define CLK_INFRA_AP_MSDC0 88
#define CLK_INFRA_MD_MSDC0 89
#define CLK_INFRA_USB 90
#define CLK_INFRA_DEVMPU_BCLK 91
#define CLK_INFRA_CCIF2_AP 92
#define CLK_INFRA_CCIF2_MD 93
#define CLK_INFRA_CCIF3_AP 94
#define CLK_INFRA_CCIF3_MD 95
#define CLK_INFRA_SEJ_F13M 96
#define CLK_INFRA_AES_BCLK 97
#define CLK_INFRA_I2C7 98
#define CLK_INFRA_I2C8 99
#define CLK_INFRA_FBIST2FPC 100
#define CLK_INFRA_NR_CLK 101
/* MFGCFG */
#define CLK_MFG_BG3D 0
#define CLK_MFG_NR_CLK 1
/* IMG */
#define CLK_IMG_OWE 0
#define CLK_IMG_WPE_B 1
#define CLK_IMG_WPE_A 2
#define CLK_IMG_MFB 3
#define CLK_IMG_RSC 4
#define CLK_IMG_DPE 5
#define CLK_IMG_FDVT 6
#define CLK_IMG_DIP 7
#define CLK_IMG_LARB2 8
#define CLK_IMG_LARB5 9
#define CLK_IMG_NR_CLK 10
/* MMSYS_CONFIG */
#define CLK_MM_SMI_COMMON 0
#define CLK_MM_SMI_LARB0 1
#define CLK_MM_SMI_LARB1 2
#define CLK_MM_GALS_COMM0 3
#define CLK_MM_GALS_COMM1 4
#define CLK_MM_GALS_CCU2MM 5
#define CLK_MM_GALS_IPU12MM 6
#define CLK_MM_GALS_IMG2MM 7
#define CLK_MM_GALS_CAM2MM 8
#define CLK_MM_GALS_IPU2MM 9
#define CLK_MM_MDP_DL_TXCK 10
#define CLK_MM_IPU_DL_TXCK 11
#define CLK_MM_MDP_RDMA0 12
#define CLK_MM_MDP_RDMA1 13
#define CLK_MM_MDP_RSZ0 14
#define CLK_MM_MDP_RSZ1 15
#define CLK_MM_MDP_TDSHP 16
#define CLK_MM_MDP_WROT0 17
#define CLK_MM_FAKE_ENG 18
#define CLK_MM_DISP_OVL0 19
#define CLK_MM_DISP_OVL0_2L 20
#define CLK_MM_DISP_OVL1_2L 21
#define CLK_MM_DISP_RDMA0 22
#define CLK_MM_DISP_RDMA1 23
#define CLK_MM_DISP_WDMA0 24
#define CLK_MM_DISP_COLOR0 25
#define CLK_MM_DISP_CCORR0 26
#define CLK_MM_DISP_AAL0 27
#define CLK_MM_DISP_GAMMA0 28
#define CLK_MM_DISP_DITHER0 29
#define CLK_MM_DISP_SPLIT 30
#define CLK_MM_DSI0_MM 31
#define CLK_MM_DSI0_IF 32
#define CLK_MM_DPI_MM 33
#define CLK_MM_DPI_IF 34
#define CLK_MM_FAKE_ENG2 35
#define CLK_MM_MDP_DL_RX 36
#define CLK_MM_IPU_DL_RX 37
#define CLK_MM_26M 38
#define CLK_MM_MMSYS_R2Y 39
#define CLK_MM_DISP_RSZ 40
#define CLK_MM_MDP_WDMA0 41
#define CLK_MM_MDP_AAL 42
#define CLK_MM_MDP_CCORR 43
#define CLK_MM_DBI_MM 44
#define CLK_MM_DBI_IF 45
#define CLK_MM_NR_CLK 46
/* VDEC_GCON */
#define CLK_VDEC_VDEC 0
#define CLK_VDEC_LARB1 1
#define CLK_VDEC_NR_CLK 2
/* VENC_GCON */
#define CLK_VENC_LARB 0
#define CLK_VENC_VENC 1
#define CLK_VENC_JPGENC 2
#define CLK_VENC_NR_CLK 3
/* AUDIO */
#define CLK_AUDIO_TML 0
#define CLK_AUDIO_DAC_PREDIS 1
#define CLK_AUDIO_DAC 2
#define CLK_AUDIO_ADC 3
#define CLK_AUDIO_APLL_TUNER 4
#define CLK_AUDIO_APLL2_TUNER 5
#define CLK_AUDIO_24M 6
#define CLK_AUDIO_22M 7
#define CLK_AUDIO_AFE 8
#define CLK_AUDIO_I2S4 9
#define CLK_AUDIO_I2S3 10
#define CLK_AUDIO_I2S2 11
#define CLK_AUDIO_I2S1 12
#define CLK_AUDIO_PDN_ADDA6_ADC 13
#define CLK_AUDIO_TDM 14
#define CLK_AUDIO_NR_CLK 15
/* IPU_CONN */
#define CLK_IPU_CONN_IPU 0
#define CLK_IPU_CONN_AHB 1
#define CLK_IPU_CONN_AXI 2
#define CLK_IPU_CONN_ISP 3
#define CLK_IPU_CONN_CAM_ADL 4
#define CLK_IPU_CONN_IMG_ADL 5
#define CLK_IPU_CONN_DAP_RX 6
#define CLK_IPU_CONN_APB2AXI 7
#define CLK_IPU_CONN_APB2AHB 8
#define CLK_IPU_CONN_IPU_CAB1TO2 9
#define CLK_IPU_CONN_IPU1_CAB1TO2 10
#define CLK_IPU_CONN_IPU2_CAB1TO2 11
#define CLK_IPU_CONN_CAB3TO3 12
#define CLK_IPU_CONN_CAB2TO1 13
#define CLK_IPU_CONN_CAB3TO1_SLICE 14
#define CLK_IPU_CONN_NR_CLK 15
/* IPU_ADL */
#define CLK_IPU_ADL_CABGEN 0
#define CLK_IPU_ADL_NR_CLK 1
/* IPU_CORE0 */
#define CLK_IPU_CORE0_JTAG 0
#define CLK_IPU_CORE0_AXI 1
#define CLK_IPU_CORE0_IPU 2
#define CLK_IPU_CORE0_NR_CLK 3
/* IPU_CORE1 */
#define CLK_IPU_CORE1_JTAG 0
#define CLK_IPU_CORE1_AXI 1
#define CLK_IPU_CORE1_IPU 2
#define CLK_IPU_CORE1_NR_CLK 3
/* MCUCFG */
#define CLK_MCU_MP0_SEL 0
#define CLK_MCU_MP2_SEL 1
#define CLK_MCU_BUS_SEL 2
#define CLK_MCU_NR_CLK 3
#endif /* _DT_BINDINGS_CLK_MT8183_H */

211
include/dt-bindings/clock/mt8516-clk.h Normal file
View File

@@ -0,0 +1,211 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
* Copyright (c) 2019 BayLibre, SAS.
* Author: James Liao <jamesjj.liao@mediatek.com>
*/
#ifndef _DT_BINDINGS_CLK_MT8516_H
#define _DT_BINDINGS_CLK_MT8516_H
/* APMIXEDSYS */
#define CLK_APMIXED_ARMPLL 0
#define CLK_APMIXED_MAINPLL 1
#define CLK_APMIXED_UNIVPLL 2
#define CLK_APMIXED_MMPLL 3
#define CLK_APMIXED_APLL1 4
#define CLK_APMIXED_APLL2 5
#define CLK_APMIXED_NR_CLK 6
/* INFRACFG */
#define CLK_IFR_MUX1_SEL 0
#define CLK_IFR_ETH_25M_SEL 1
#define CLK_IFR_I2C0_SEL 2
#define CLK_IFR_I2C1_SEL 3
#define CLK_IFR_I2C2_SEL 4
#define CLK_IFR_NR_CLK 5
/* TOPCKGEN */
#define CLK_TOP_CLK_NULL 0
#define CLK_TOP_I2S_INFRA_BCK 1
#define CLK_TOP_MEMPLL 2
#define CLK_TOP_DMPLL 3
#define CLK_TOP_MAINPLL_D2 4
#define CLK_TOP_MAINPLL_D4 5
#define CLK_TOP_MAINPLL_D8 6
#define CLK_TOP_MAINPLL_D16 7
#define CLK_TOP_MAINPLL_D11 8
#define CLK_TOP_MAINPLL_D22 9
#define CLK_TOP_MAINPLL_D3 10
#define CLK_TOP_MAINPLL_D6 11
#define CLK_TOP_MAINPLL_D12 12
#define CLK_TOP_MAINPLL_D5 13
#define CLK_TOP_MAINPLL_D10 14
#define CLK_TOP_MAINPLL_D20 15
#define CLK_TOP_MAINPLL_D40 16
#define CLK_TOP_MAINPLL_D7 17
#define CLK_TOP_MAINPLL_D14 18
#define CLK_TOP_UNIVPLL_D2 19
#define CLK_TOP_UNIVPLL_D4 20
#define CLK_TOP_UNIVPLL_D8 21
#define CLK_TOP_UNIVPLL_D16 22
#define CLK_TOP_UNIVPLL_D3 23
#define CLK_TOP_UNIVPLL_D6 24
#define CLK_TOP_UNIVPLL_D12 25
#define CLK_TOP_UNIVPLL_D24 26
#define CLK_TOP_UNIVPLL_D5 27
#define CLK_TOP_UNIVPLL_D20 28
#define CLK_TOP_MMPLL380M 29
#define CLK_TOP_MMPLL_D2 30
#define CLK_TOP_MMPLL_200M 31
#define CLK_TOP_USB_PHY48M 32
#define CLK_TOP_APLL1 33
#define CLK_TOP_APLL1_D2 34
#define CLK_TOP_APLL1_D4 35
#define CLK_TOP_APLL1_D8 36
#define CLK_TOP_APLL2 37
#define CLK_TOP_APLL2_D2 38
#define CLK_TOP_APLL2_D4 39
#define CLK_TOP_APLL2_D8 40
#define CLK_TOP_CLK26M 41
#define CLK_TOP_CLK26M_D2 42
#define CLK_TOP_AHB_INFRA_D2 43
#define CLK_TOP_NFI1X 44
#define CLK_TOP_ETH_D2 45
#define CLK_TOP_THEM 46
#define CLK_TOP_APDMA 47
#define CLK_TOP_I2C0 48
#define CLK_TOP_I2C1 49
#define CLK_TOP_AUXADC1 50
#define CLK_TOP_NFI 51
#define CLK_TOP_NFIECC 52
#define CLK_TOP_DEBUGSYS 53
#define CLK_TOP_PWM 54
#define CLK_TOP_UART0 55
#define CLK_TOP_UART1 56
#define CLK_TOP_BTIF 57
#define CLK_TOP_USB 58
#define CLK_TOP_FLASHIF_26M 59
#define CLK_TOP_AUXADC2 60
#define CLK_TOP_I2C2 61
#define CLK_TOP_MSDC0 62
#define CLK_TOP_MSDC1 63
#define CLK_TOP_NFI2X 64
#define CLK_TOP_PMICWRAP_AP 65
#define CLK_TOP_SEJ 66
#define CLK_TOP_MEMSLP_DLYER 67
#define CLK_TOP_SPI 68
#define CLK_TOP_APXGPT 69
#define CLK_TOP_AUDIO 70
#define CLK_TOP_PMICWRAP_MD 71
#define CLK_TOP_PMICWRAP_CONN 72
#define CLK_TOP_PMICWRAP_26M 73
#define CLK_TOP_AUX_ADC 74
#define CLK_TOP_AUX_TP 75
#define CLK_TOP_MSDC2 76
#define CLK_TOP_RBIST 77
#define CLK_TOP_NFI_BUS 78
#define CLK_TOP_GCE 79
#define CLK_TOP_TRNG 80
#define CLK_TOP_SEJ_13M 81
#define CLK_TOP_AES 82
#define CLK_TOP_PWM_B 83
#define CLK_TOP_PWM1_FB 84
#define CLK_TOP_PWM2_FB 85
#define CLK_TOP_PWM3_FB 86
#define CLK_TOP_PWM4_FB 87
#define CLK_TOP_PWM5_FB 88
#define CLK_TOP_USB_1P 89
#define CLK_TOP_FLASHIF_FREERUN 90
#define CLK_TOP_66M_ETH 91
#define CLK_TOP_133M_ETH 92
#define CLK_TOP_FETH_25M 93
#define CLK_TOP_FETH_50M 94
#define CLK_TOP_FLASHIF_AXI 95
#define CLK_TOP_USBIF 96
#define CLK_TOP_UART2 97
#define CLK_TOP_BSI 98
#define CLK_TOP_RG_SPINOR 99
#define CLK_TOP_RG_MSDC2 100
#define CLK_TOP_RG_ETH 101
#define CLK_TOP_RG_AUD1 102
#define CLK_TOP_RG_AUD2 103
#define CLK_TOP_RG_AUD_ENGEN1 104
#define CLK_TOP_RG_AUD_ENGEN2 105
#define CLK_TOP_RG_I2C 106
#define CLK_TOP_RG_PWM_INFRA 107
#define CLK_TOP_RG_AUD_SPDIF_IN 108
#define CLK_TOP_RG_UART2 109
#define CLK_TOP_RG_BSI 110
#define CLK_TOP_RG_DBG_ATCLK 111
#define CLK_TOP_RG_NFIECC 112
#define CLK_TOP_RG_APLL1_D2_EN 113
#define CLK_TOP_RG_APLL1_D4_EN 114
#define CLK_TOP_RG_APLL1_D8_EN 115
#define CLK_TOP_RG_APLL2_D2_EN 116
#define CLK_TOP_RG_APLL2_D4_EN 117
#define CLK_TOP_RG_APLL2_D8_EN 118
#define CLK_TOP_APLL12_DIV0 119
#define CLK_TOP_APLL12_DIV1 120
#define CLK_TOP_APLL12_DIV2 121
#define CLK_TOP_APLL12_DIV3 122
#define CLK_TOP_APLL12_DIV4 123
#define CLK_TOP_APLL12_DIV4B 124
#define CLK_TOP_APLL12_DIV5 125
#define CLK_TOP_APLL12_DIV5B 126
#define CLK_TOP_APLL12_DIV6 127
#define CLK_TOP_UART0_SEL 128
#define CLK_TOP_EMI_DDRPHY_SEL 129
#define CLK_TOP_AHB_INFRA_SEL 130
#define CLK_TOP_MSDC0_SEL 131
#define CLK_TOP_UART1_SEL 132
#define CLK_TOP_MSDC1_SEL 133
#define CLK_TOP_PMICSPI_SEL 134
#define CLK_TOP_QAXI_AUD26M_SEL 135
#define CLK_TOP_AUD_INTBUS_SEL 136
#define CLK_TOP_NFI2X_PAD_SEL 137
#define CLK_TOP_NFI1X_PAD_SEL 138
#define CLK_TOP_DDRPHYCFG_SEL 139
#define CLK_TOP_USB_78M_SEL 140
#define CLK_TOP_SPINOR_SEL 141
#define CLK_TOP_MSDC2_SEL 142
#define CLK_TOP_ETH_SEL 143
#define CLK_TOP_AUD1_SEL 144
#define CLK_TOP_AUD2_SEL 145
#define CLK_TOP_AUD_ENGEN1_SEL 146
#define CLK_TOP_AUD_ENGEN2_SEL 147
#define CLK_TOP_I2C_SEL 148
#define CLK_TOP_AUD_I2S0_M_SEL 149
#define CLK_TOP_AUD_I2S1_M_SEL 150
#define CLK_TOP_AUD_I2S2_M_SEL 151
#define CLK_TOP_AUD_I2S3_M_SEL 152
#define CLK_TOP_AUD_I2S4_M_SEL 153
#define CLK_TOP_AUD_I2S5_M_SEL 154
#define CLK_TOP_AUD_SPDIF_B_SEL 155
#define CLK_TOP_PWM_SEL 156
#define CLK_TOP_SPI_SEL 157
#define CLK_TOP_AUD_SPDIFIN_SEL 158
#define CLK_TOP_UART2_SEL 159
#define CLK_TOP_BSI_SEL 160
#define CLK_TOP_DBG_ATCLK_SEL 161
#define CLK_TOP_CSW_NFIECC_SEL 162
#define CLK_TOP_NFIECC_SEL 163
#define CLK_TOP_APLL12_CK_DIV0 164
#define CLK_TOP_APLL12_CK_DIV1 165
#define CLK_TOP_APLL12_CK_DIV2 166
#define CLK_TOP_APLL12_CK_DIV3 167
#define CLK_TOP_APLL12_CK_DIV4 168
#define CLK_TOP_APLL12_CK_DIV4B 169
#define CLK_TOP_APLL12_CK_DIV5 170
#define CLK_TOP_APLL12_CK_DIV5B 171
#define CLK_TOP_APLL12_CK_DIV6 172
#define CLK_TOP_USB_78M 173
#define CLK_TOP_MSDC0_INFRA 174
#define CLK_TOP_MSDC1_INFRA 175
#define CLK_TOP_MSDC2_INFRA 176
#define CLK_TOP_NR_CLK 177
#endif /* _DT_BINDINGS_CLK_MT8516_H */

5
include/dt-bindings/clock/qcom,gcc-qcs404.h
View File

@@ -146,6 +146,10 @@
#define GCC_MDP_TBU_CLK 138
#define GCC_QDSS_DAP_CLK 139
#define GCC_DCC_XO_CLK 140
#define GCC_CDSP_CFG_AHB_CLK 143
#define GCC_BIMC_CDSP_CLK 144
#define GCC_CDSP_TBU_CLK 145
#define GCC_CDSP_BIMC_CLK_SRC 146
#define GCC_GENI_IR_BCR 0
#define GCC_USB_HS_BCR 1
@@ -161,5 +165,6 @@
#define GCC_PCIE_0_LINK_DOWN_BCR 11
#define GCC_PCIEPHY_0_PHY_BCR 12
#define GCC_EMAC_BCR 13
#define GCC_CDSP_RESTART 14
#endif

15
include/dt-bindings/clock/qcom,turingcc-qcs404.h Normal file
View File

@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019, Linaro Ltd
*/
#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H
#define _DT_BINDINGS_CLK_TURING_QCS404_H
#define TURING_Q6SS_Q6_AXIM_CLK 0
#define TURING_Q6SS_AHBM_AON_CLK 1
#define TURING_WRAPPER_AON_CLK 2
#define TURING_Q6SS_AHBS_AON_CLK 3
#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4
#endif

7
include/dt-bindings/clock/stm32fx-clock.h
View File

@@ -54,7 +54,10 @@
#define CLK_I2C3 28
#define CLK_I2C4 29
#define CLK_LPTIMER 30
#define END_PRIMARY_CLK_F7 31
#define CLK_PLL_SRC 31
#define CLK_DFSDM1 32
#define CLK_ADFSDM1 33
#define CLK_F769_DSI 34
#define END_PRIMARY_CLK_F7 35
#endif

2
include/dt-bindings/clock/sun5i-ccu.h
View File

@@ -100,7 +100,7 @@
#define CLK_AVS 96
#define CLK_HDMI 97
#define CLK_GPU 98
#define CLK_MBUS 99
#define CLK_IEP 100
#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */

26
include/dt-bindings/clock/xlnx,zynqmp-clk.h → include/dt-bindings/clock/xlnx-zynqmp-clk.h
View File

@@ -54,14 +54,14 @@
#define IOU_SWITCH 42
#define GEM_TSU_REF 43
#define GEM_TSU 44
#define GEM0_REF 45
#define GEM1_REF 46
#define GEM2_REF 47
#define GEM3_REF 48
#define GEM0_TX 49
#define GEM1_TX 50
#define GEM2_TX 51
#define GEM3_TX 52
#define GEM0_TX 45
#define GEM1_TX 46
#define GEM2_TX 47
#define GEM3_TX 48
#define GEM0_RX 49
#define GEM1_RX 50
#define GEM2_RX 51
#define GEM3_RX 52
#define QSPI_REF 53
#define SDIO0_REF 54
#define SDIO1_REF 55
@@ -112,5 +112,15 @@
#define VPLL_POST_SRC 100
#define CAN0_MIO 101
#define CAN1_MIO 102
#define ACPU_FULL 103
#define GEM0_REF 104
#define GEM1_REF 105
#define GEM2_REF 106
#define GEM3_REF 107
#define GEM0_REF_UNG 108
#define GEM1_REF_UNG 109
#define GEM2_REF_UNG 110
#define GEM3_REF_UNG 111
#define LPD_WDT 112
#endif

25
include/dt-bindings/firmware/imx/rsrc.h
View File

@@ -36,15 +36,11 @@
#define IMX_SC_R_DC_0_BLIT1 20
#define IMX_SC_R_DC_0_BLIT2 21
#define IMX_SC_R_DC_0_BLIT_OUT 22
#define IMX_SC_R_DC_0_CAPTURE0 23
#define IMX_SC_R_DC_0_CAPTURE1 24
#define IMX_SC_R_PERF 23
#define IMX_SC_R_DC_0_WARP 25
#define IMX_SC_R_DC_0_INTEGRAL0 26
#define IMX_SC_R_DC_0_INTEGRAL1 27
#define IMX_SC_R_DC_0_VIDEO0 28
#define IMX_SC_R_DC_0_VIDEO1 29
#define IMX_SC_R_DC_0_FRAC0 30
#define IMX_SC_R_DC_0_FRAC1 31
#define IMX_SC_R_DC_0 32
#define IMX_SC_R_GPU_2_PID0 33
#define IMX_SC_R_DC_0_PLL_0 34
@@ -53,17 +49,11 @@
#define IMX_SC_R_DC_1_BLIT1 37
#define IMX_SC_R_DC_1_BLIT2 38
#define IMX_SC_R_DC_1_BLIT_OUT 39
#define IMX_SC_R_DC_1_CAPTURE0 40
#define IMX_SC_R_DC_1_CAPTURE1 41
#define IMX_SC_R_DC_1_WARP 42
#define IMX_SC_R_DC_1_INTEGRAL0 43
#define IMX_SC_R_DC_1_INTEGRAL1 44
#define IMX_SC_R_DC_1_VIDEO0 45
#define IMX_SC_R_DC_1_VIDEO1 46
#define IMX_SC_R_DC_1_FRAC0 47
#define IMX_SC_R_DC_1_FRAC1 48
#define IMX_SC_R_DC_1 49
#define IMX_SC_R_GPU_3_PID0 50
#define IMX_SC_R_DC_1_PLL_0 51
#define IMX_SC_R_DC_1_PLL_1 52
#define IMX_SC_R_SPI_0 53
@@ -303,8 +293,6 @@
#define IMX_SC_R_M4_0_UART 287
#define IMX_SC_R_M4_0_I2C 288
#define IMX_SC_R_M4_0_INTMUX 289
#define IMX_SC_R_M4_0_SIM 290
#define IMX_SC_R_M4_0_WDOG 291
#define IMX_SC_R_M4_0_MU_0B 292
#define IMX_SC_R_M4_0_MU_0A0 293
#define IMX_SC_R_M4_0_MU_0A1 294
@@ -323,8 +311,6 @@
#define IMX_SC_R_M4_1_UART 307
#define IMX_SC_R_M4_1_I2C 308
#define IMX_SC_R_M4_1_INTMUX 309
#define IMX_SC_R_M4_1_SIM 310
#define IMX_SC_R_M4_1_WDOG 311
#define IMX_SC_R_M4_1_MU_0B 312
#define IMX_SC_R_M4_1_MU_0A0 313
#define IMX_SC_R_M4_1_MU_0A1 314
@@ -337,7 +323,7 @@
#define IMX_SC_R_IRQSTR_SCU2 321
#define IMX_SC_R_IRQSTR_DSP 322
#define IMX_SC_R_ELCDIF_PLL 323
#define IMX_SC_R_UNUSED6 324
#define IMX_SC_R_OCRAM 324
#define IMX_SC_R_AUDIO_PLL_0 325
#define IMX_SC_R_PI_0 326
#define IMX_SC_R_PI_0_PWM_0 327
@@ -554,6 +540,11 @@
#define IMX_SC_R_VPU_MU_3 538
#define IMX_SC_R_VPU_ENC_1 539
#define IMX_SC_R_VPU 540
#define IMX_SC_R_LAST 541
#define IMX_SC_R_DMA_5_CH0 541
#define IMX_SC_R_DMA_5_CH1 542
#define IMX_SC_R_DMA_5_CH2 543
#define IMX_SC_R_DMA_5_CH3 544
#define IMX_SC_R_ATTESTATION 545
#define IMX_SC_R_LAST 546
#endif /* __DT_BINDINGS_RSCRC_IMX_H */

16
include/dt-bindings/iio/temperature/thermocouple.h Normal file
View File

@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H
#define _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H
#define THERMOCOUPLE_TYPE_B 0x00
#define THERMOCOUPLE_TYPE_E 0x01
#define THERMOCOUPLE_TYPE_J 0x02
#define THERMOCOUPLE_TYPE_K 0x03
#define THERMOCOUPLE_TYPE_N 0x04
#define THERMOCOUPLE_TYPE_R 0x05
#define THERMOCOUPLE_TYPE_S 0x06
#define THERMOCOUPLE_TYPE_T 0x07
#endif /* _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H */

13
include/dt-bindings/phy/phy-am654-serdes.h Normal file
View File

@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for AM654 SERDES.
*/
#ifndef _DT_BINDINGS_AM654_SERDES
#define _DT_BINDINGS_AM654_SERDES
#define AM654_SERDES_CMU_REFCLK 0
#define AM654_SERDES_LO_REFCLK 1
#define AM654_SERDES_RO_REFCLK 2
#endif /* _DT_BINDINGS_AM654_SERDES */

130
include/dt-bindings/pinctrl/am33xx.h
View File

@@ -40,5 +40,133 @@
#undef PIN_OFF_INPUT_PULLDOWN
#undef PIN_OFF_WAKEUPENABLE
#endif
#define AM335X_PIN_OFFSET_MIN 0x0800U
#define AM335X_PIN_GPMC_AD0 0x800
#define AM335X_PIN_GPMC_AD1 0x804
#define AM335X_PIN_GPMC_AD2 0x808
#define AM335X_PIN_GPMC_AD3 0x80c
#define AM335X_PIN_GPMC_AD4 0x810
#define AM335X_PIN_GPMC_AD5 0x814
#define AM335X_PIN_GPMC_AD6 0x818
#define AM335X_PIN_GPMC_AD7 0x81c
#define AM335X_PIN_GPMC_AD8 0x820
#define AM335X_PIN_GPMC_AD9 0x824
#define AM335X_PIN_GPMC_AD10 0x828
#define AM335X_PIN_GPMC_AD11 0x82c
#define AM335X_PIN_GPMC_AD12 0x830
#define AM335X_PIN_GPMC_AD13 0x834
#define AM335X_PIN_GPMC_AD14 0x838
#define AM335X_PIN_GPMC_AD15 0x83c
#define AM335X_PIN_GPMC_A0 0x840
#define AM335X_PIN_GPMC_A1 0x844
#define AM335X_PIN_GPMC_A2 0x848
#define AM335X_PIN_GPMC_A3 0x84c
#define AM335X_PIN_GPMC_A4 0x850
#define AM335X_PIN_GPMC_A5 0x854
#define AM335X_PIN_GPMC_A6 0x858
#define AM335X_PIN_GPMC_A7 0x85c
#define AM335X_PIN_GPMC_A8 0x860
#define AM335X_PIN_GPMC_A9 0x864
#define AM335X_PIN_GPMC_A10 0x868
#define AM335X_PIN_GPMC_A11 0x86c
#define AM335X_PIN_GPMC_WAIT0 0x870
#define AM335X_PIN_GPMC_WPN 0x874
#define AM335X_PIN_GPMC_BEN1 0x878
#define AM335X_PIN_GPMC_CSN0 0x87c
#define AM335X_PIN_GPMC_CSN1 0x880
#define AM335X_PIN_GPMC_CSN2 0x884
#define AM335X_PIN_GPMC_CSN3 0x888
#define AM335X_PIN_GPMC_CLK 0x88c
#define AM335X_PIN_GPMC_ADVN_ALE 0x890
#define AM335X_PIN_GPMC_OEN_REN 0x894
#define AM335X_PIN_GPMC_WEN 0x898
#define AM335X_PIN_GPMC_BEN0_CLE 0x89c
#define AM335X_PIN_LCD_DATA0 0x8a0
#define AM335X_PIN_LCD_DATA1 0x8a4
#define AM335X_PIN_LCD_DATA2 0x8a8
#define AM335X_PIN_LCD_DATA3 0x8ac
#define AM335X_PIN_LCD_DATA4 0x8b0
#define AM335X_PIN_LCD_DATA5 0x8b4
#define AM335X_PIN_LCD_DATA6 0x8b8
#define AM335X_PIN_LCD_DATA7 0x8bc
#define AM335X_PIN_LCD_DATA8 0x8c0
#define AM335X_PIN_LCD_DATA9 0x8c4
#define AM335X_PIN_LCD_DATA10 0x8c8
#define AM335X_PIN_LCD_DATA11 0x8cc
#define AM335X_PIN_LCD_DATA12 0x8d0
#define AM335X_PIN_LCD_DATA13 0x8d4
#define AM335X_PIN_LCD_DATA14 0x8d8
#define AM335X_PIN_LCD_DATA15 0x8dc
#define AM335X_PIN_LCD_VSYNC 0x8e0
#define AM335X_PIN_LCD_HSYNC 0x8e4
#define AM335X_PIN_LCD_PCLK 0x8e8
#define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec
#define AM335X_PIN_MMC0_DAT3 0x8f0
#define AM335X_PIN_MMC0_DAT2 0x8f4
#define AM335X_PIN_MMC0_DAT1 0x8f8
#define AM335X_PIN_MMC0_DAT0 0x8fc
#define AM335X_PIN_MMC0_CLK 0x900
#define AM335X_PIN_MMC0_CMD 0x904
#define AM335X_PIN_MII1_COL 0x908
#define AM335X_PIN_MII1_CRS 0x90c
#define AM335X_PIN_MII1_RX_ER 0x910
#define AM335X_PIN_MII1_TX_EN 0x914
#define AM335X_PIN_MII1_RX_DV 0x918
#define AM335X_PIN_MII1_TXD3 0x91c
#define AM335X_PIN_MII1_TXD2 0x920
#define AM335X_PIN_MII1_TXD1 0x924
#define AM335X_PIN_MII1_TXD0 0x928
#define AM335X_PIN_MII1_TX_CLK 0x92c
#define AM335X_PIN_MII1_RX_CLK 0x930
#define AM335X_PIN_MII1_RXD3 0x934
#define AM335X_PIN_MII1_RXD2 0x938
#define AM335X_PIN_MII1_RXD1 0x93c
#define AM335X_PIN_MII1_RXD0 0x940
#define AM335X_PIN_RMII1_REF_CLK 0x944
#define AM335X_PIN_MDIO 0x948
#define AM335X_PIN_MDC 0x94c
#define AM335X_PIN_SPI0_SCLK 0x950
#define AM335X_PIN_SPI0_D0 0x954
#define AM335X_PIN_SPI0_D1 0x958
#define AM335X_PIN_SPI0_CS0 0x95c
#define AM335X_PIN_SPI0_CS1 0x960
#define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964
#define AM335X_PIN_UART0_CTSN 0x968
#define AM335X_PIN_UART0_RTSN 0x96c
#define AM335X_PIN_UART0_RXD 0x970
#define AM335X_PIN_UART0_TXD 0x974
#define AM335X_PIN_UART1_CTSN 0x978
#define AM335X_PIN_UART1_RTSN 0x97c
#define AM335X_PIN_UART1_RXD 0x980
#define AM335X_PIN_UART1_TXD 0x984
#define AM335X_PIN_I2C0_SDA 0x988
#define AM335X_PIN_I2C0_SCL 0x98c
#define AM335X_PIN_MCASP0_ACLKX 0x990
#define AM335X_PIN_MCASP0_FSX 0x994
#define AM335X_PIN_MCASP0_AXR0 0x998
#define AM335X_PIN_MCASP0_AHCLKR 0x99c
#define AM335X_PIN_MCASP0_ACLKR 0x9a0
#define AM335X_PIN_MCASP0_FSR 0x9a4
#define AM335X_PIN_MCASP0_AXR1 0x9a8
#define AM335X_PIN_MCASP0_AHCLKX 0x9ac
#define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0
#define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4
#define AM335X_PIN_WARMRSTN 0x9b8
#define AM335X_PIN_NNMI 0x9c0
#define AM335X_PIN_TMS 0x9d0
#define AM335X_PIN_TDI 0x9d4
#define AM335X_PIN_TDO 0x9d8
#define AM335X_PIN_TCK 0x9dc
#define AM335X_PIN_TRSTN 0x9e0
#define AM335X_PIN_EMU0 0x9e4
#define AM335X_PIN_EMU1 0x9e8
#define AM335X_PIN_RTC_PWRONRSTN 0x9f8
#define AM335X_PIN_PMIC_POWER_EN 0x9fc
#define AM335X_PIN_EXT_WAKEUP 0xa00
#define AM335X_PIN_USB0_DRVVBUS 0xa1c
#define AM335X_PIN_USB1_DRVVBUS 0xa34
#define AM335X_PIN_OFFSET_MAX 0x0a34U
#endif

1
include/dt-bindings/pinctrl/omap.h
View File

@@ -65,6 +65,7 @@
#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define AM33XX_PADCONF(pa, dir, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) ((dir) | (mux))
/*
* Macros to allow using the offset from the padconf physical address

6
include/dt-bindings/pinctrl/stm32-pinfunc.h
View File

@@ -32,5 +32,11 @@
#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
/* package information */
#define STM32MP_PKG_AA 0x1
#define STM32MP_PKG_AB 0x2
#define STM32MP_PKG_AC 0x4
#define STM32MP_PKG_AD 0x8
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */

1
include/dt-bindings/power/r8a77965-sysc.h
View File

@@ -21,7 +21,6 @@
#define R8A77965_PD_A3VC 14
#define R8A77965_PD_3DG_A 17
#define R8A77965_PD_3DG_B 18
#define R8A77965_PD_A3IR 24
#define R8A77965_PD_A2VC1 26
/* Always-on power area */

8
include/dt-bindings/thermal/tegra124-soctherm.h
View File

@@ -12,9 +12,9 @@
#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
#define TEGRA124_SOCTHERM_SENSOR_NUM 4
#define TEGRA_SOCTHERM_THROT_LEVEL_LOW 0
#define TEGRA_SOCTHERM_THROT_LEVEL_MED 1
#define TEGRA_SOCTHERM_THROT_LEVEL_HIGH 2
#define TEGRA_SOCTHERM_THROT_LEVEL_NONE -1
#define TEGRA_SOCTHERM_THROT_LEVEL_NONE 0
#define TEGRA_SOCTHERM_THROT_LEVEL_LOW 1
#define TEGRA_SOCTHERM_THROT_LEVEL_MED 2
#define TEGRA_SOCTHERM_THROT_LEVEL_HIGH 3
#endif