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powerpc/mpc85xx: Add BSC9132 QDS Support

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- BSC9132 is an integrated device that targets Femto base station market.
  It combines Power Architecture e500v2 and DSP StarCore SC3850 technologies
  with MAPLE-B2F baseband acceleration processing elements

- BSC9132QDS Overview
     2Gbyte DDR3 (on board DDR)
     32Mbyte 16bit NOR flash
     128Mbyte 2K page size NAND Flash
     256 Kbit M24256 I2C EEPROM
     128 Mbit SPI Flash memory
     SD slot
     eTSEC1: Connected to SGMII PHY
     eTSEC2: Connected to SGMII PHY
     DUART interface: supports one UARTs up to 115200 bps for console display

Signed-off-by: Harninder Rai <harninder.rai@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
harninder rai
2014-05-15 13:15:33 +05:30
committed by Scott Wood
parent fd7e5b7a87
commit 1be62c6cce
8 changed files with 488 additions and 0 deletions
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35
arch/powerpc/boot/dts/bsc9132qds.dts Normal file
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/*
* BSC9132 QDS Device Tree Source
*
* Copyright 2014 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "fsl/bsc9132si-pre.dtsi"
/ {
model = "fsl,bsc9132qds";
compatible = "fsl,bsc9132qds";
memory {
device_type = "memory";
};
ifc: ifc@ff71e000 {
/* NOR, NAND Flash on board */
ranges = <0x0 0x0 0x0 0x88000000 0x08000000
0x1 0x0 0x0 0xff800000 0x00010000>;
reg = <0x0 0xff71e000 0x0 0x2000>;
};
soc: soc@ff700000 {
ranges = <0x0 0x0 0xff700000 0x100000>;
};
};
/include/ "bsc9132qds.dtsi"
/include/ "fsl/bsc9132si-post.dtsi"

101
arch/powerpc/boot/dts/bsc9132qds.dtsi Normal file
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/*
* BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&ifc {
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,ifc-nand";
reg = <0x1 0x0 0x4000>;
};
};
&soc {
spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <30000000>;
};
};
i2c@3000 {
fpga: fpga@66 {
compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
reg = <0x66>;
};
};
usb@22000 {
phy_type = "ulpi";
};
mdio@24000 {
phy0: ethernet-phy@0 {
reg = <0x0>;
};
phy1: ethernet-phy@1 {
reg = <0x1>;
};
tbi0: tbi-phy@11 {
reg = <0x1f>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
};
enet1: ethernet@b1000 {
phy-handle = <&phy1>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
};
};

185
arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi Normal file
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/*
* BSC9132 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&ifc {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,ifc", "simple-bus";
/* FIXME: Test whether interrupts are split */
interrupts = <16 2 0 0 20 2 0 0>;
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,bsc9132-immr", "simple-bus";
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,bsc9132-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <16 2 0 0>;
};
memory-controller@2000 {
compatible = "fsl,bsc9132-memory-controller";
reg = <0x2000 0x1000>;
interrupts = <16 2 1 8>;
};
/include/ "pq3-i2c-0.dtsi"
i2c@3000 {
interrupts = <17 2 0 0>;
};
/include/ "pq3-i2c-1.dtsi"
i2c@3100 {
interrupts = <17 2 0 0>;
};
/include/ "pq3-duart-0.dtsi"
serial0: serial@4500 {
interrupts = <18 2 0 0>;
};
serial1: serial@4600 {
interrupts = <18 2 0 0 >;
};
/include/ "pq3-espi-0.dtsi"
spi0: spi@7000 {
fsl,espi-num-chipselects = <1>;
interrupts = <22 0x2 0 0>;
};
/include/ "pq3-gpio-0.dtsi"
gpio-controller@f000 {
interrupts = <19 0x2 0 0>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,bsc9132-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2,256K
interrupts = <16 2 1 0>;
};
/include/ "pq3-dma-0.dtsi"
dma@21300 {
dma-channel@0 {
interrupts = <62 2 0 0>;
};
dma-channel@80 {
interrupts = <63 2 0 0>;
};
dma-channel@100 {
interrupts = <64 2 0 0>;
};
dma-channel@180 {
interrupts = <65 2 0 0>;
};
};
/include/ "pq3-usb2-dr-0.dtsi"
usb@22000 {
compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
interrupts = <40 0x2 0 0>;
};
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
fsl,sdhci-auto-cmd12;
interrupts = <41 0x2 0 0>;
};
/include/ "pq3-sec4.4-0.dtsi"
crypto@30000 {
interrupts = <57 2 0 0>;
sec_jr0: jr@1000 {
interrupts = <58 2 0 0>;
};
sec_jr1: jr@2000 {
interrupts = <59 2 0 0>;
};
sec_jr2: jr@3000 {
interrupts = <60 2 0 0>;
};
sec_jr3: jr@4000 {
interrupts = <61 2 0 0>;
};
};
/include/ "pq3-mpic.dtsi"
/include/ "pq3-mpic-timer-B.dtsi"
/include/ "pq3-etsec2-0.dtsi"
enet0: ethernet@b0000 {
queue-group@b0000 {
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
};
};
/include/ "pq3-etsec2-1.dtsi"
enet1: ethernet@b1000 {
queue-group@b1000 {
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
};
};
global-utilities@e0000 {
compatible = "fsl,bsc9132-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};

66
arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi Normal file
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/*
* BSC9132 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
serial0 = &serial0;
ethernet0 = &enet0;
ethernet1 = &enet1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e500v2@0 {
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
cpu1: PowerPC,e500v2@1 {
device_type = "cpu";
reg = <0x1>;
next-level-cache = <&L2>;
};
};
};