Merge tag 'pci-v4.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
- detach driver before tearing down procfs/sysfs (Alex Williamson)
- disable PCIe services during shutdown (Sinan Kaya)
- fix ASPM oops on systems with no Root Ports (Ard Biesheuvel)
- fix ASPM LTR_L1.2_THRESHOLD programming (Bjorn Helgaas)
- fix ASPM Common_Mode_Restore_Time computation (Bjorn Helgaas)
- fix portdrv MSI/MSI-X vector allocation (Dongdong Liu, Bjorn
Helgaas)
- report non-fatal AER errors only to the affected endpoint (Gabriele
Paoloni)
- distribute bus numbers, MMIO, and I/O space among hotplug bridges to
allow more devices to be hot-added (Mika Westerberg)
- fix pciehp races during initialization and surprise link down (Mika
Westerberg)
- handle surprise-removed devices in PME handling (Qiang)
- support resizable BARs for large graphics devices (Christian König)
- expose SR-IOV offset, stride, and VF device ID via sysfs (Filippo
Sironi)
- create SR-IOV virtfn/physfn sysfs links before attaching driver
(Stuart Hayes)
- fix SR-IOV "ARI Capable Hierarchy" restore issue (Tony Nguyen)
- enforce Kconfig IOV/REALLOC dependency (Sascha El-Sharkawy)
- avoid slot reset if bridge itself is broken (Jan Glauber)
- clean up pci_reset_function() path (Jan H. Schönherr)
- make pci_map_rom() fail if the option ROM is invalid (Changbin Du)
- convert timers to timer_setup() (Kees Cook)
- move PCI_QUIRKS to PCI bus Kconfig menu (Randy Dunlap)
- constify pci_dev_type and intel_mid_pci_ops (Bhumika Goyal)
- remove unnecessary pci_dev, pci_bus, resource, pcibios_set_master()
declarations (Bjorn Helgaas)
- fix endpoint framework overflows and BUG()s (Dan Carpenter)
- fix endpoint framework issues (Kishon Vijay Abraham I)
- avoid broken Cavium CN8xxx bus reset behavior (David Daney)
- extend Cavium ACS capability quirks (Vadim Lomovtsev)
- support Synopsys DesignWare RC in ECAM mode (Ard Biesheuvel)
- turn off dra7xx clocks cleanly on shutdown (Keerthy)
- fix Faraday probe error path (Wei Yongjun)
- support HiSilicon STB SoC PCIe host controller (Jianguo Sun)
- fix Hyper-V interrupt affinity issue (Dexuan Cui)
- remove useless ACPI warning for Hyper-V pass-through devices (Vitaly
Kuznetsov)
- support multiple MSI on iProc (Sandor Bodo-Merle)
- support Layerscape LS1012a and LS1046a PCIe host controllers (Hou
Zhiqiang)
- fix Layerscape default error response (Minghuan Lian)
- support MSI on Tango host controller (Marc Gonzalez)
- support Tegra186 PCIe host controller (Manikanta Maddireddy)
- use generic accessors on Tegra when possible (Thierry Reding)
- support V3 Semiconductor PCI host controller (Linus Walleij)
* tag 'pci-v4.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (85 commits)
PCI/ASPM: Add L1 Substates definitions
PCI/ASPM: Reformat ASPM register definitions
PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD
PCI/ASPM: Account for downstream device's Port Common_Mode_Restore_Time
PCI: xgene: Rename xgene_pcie_probe_bridge() to xgene_pcie_probe()
PCI: xilinx: Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up()
PCI: altera: Rename altera_pcie_link_is_up() to altera_pcie_link_up()
PCI: Fix kernel-doc build warning
PCI: Fail pci_map_rom() if the option ROM is invalid
PCI: Move pci_map_rom() error path
PCI: Move PCI_QUIRKS to the PCI bus menu
alpha/PCI: Make pdev_save_srm_config() static
PCI: Remove unused declarations
PCI: Remove redundant pci_dev, pci_bus, resource declarations
PCI: Remove redundant pcibios_set_master() declarations
PCI/PME: Handle invalid data when reading Root Status
PCI: hv: Use effective affinity mask
PCI: pciehp: Do not clear Presence Detect Changed during initialization
PCI: pciehp: Fix race condition handling surprise link down
PCI: Distribute available resources to hotplug-capable bridges
...
This commit is contained in:
Linus Torvalds
@@ -169,4 +169,14 @@ config PCIE_KIRIN
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Say Y here if you want PCIe controller support
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on HiSilicon Kirin series SoCs.
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config PCIE_HISI_STB
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bool "HiSilicon STB SoCs PCIe controllers"
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depends on ARCH_HISI
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depends on PCI
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIEPORTBUS
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support on HiSilicon STB SoCs
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endmenu
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@@ -15,6 +15,7 @@ obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
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obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
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obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
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obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
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# The following drivers are for devices that use the generic ACPI
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# pci_root.c driver but don't support standard ECAM config access.
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@@ -810,6 +810,22 @@ static int dra7xx_pcie_resume_noirq(struct device *dev)
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}
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#endif
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void dra7xx_pcie_shutdown(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
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int ret;
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dra7xx_pcie_stop_link(dra7xx->pci);
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ret = pm_runtime_put_sync(dev);
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if (ret < 0)
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dev_dbg(dev, "pm_runtime_put_sync failed\n");
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pm_runtime_disable(dev);
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dra7xx_pcie_disable_phy(dra7xx);
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}
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static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
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@@ -823,5 +839,6 @@ static struct platform_driver dra7xx_pcie_driver = {
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.suppress_bind_attrs = true,
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.pm = &dra7xx_pcie_pm_ops,
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},
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.shutdown = dra7xx_pcie_shutdown,
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};
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builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);
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@@ -33,6 +33,8 @@
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/* PEX Internal Configuration Registers */
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#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
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#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
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#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
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#define PCIE_IATU_NUM 6
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@@ -124,6 +126,14 @@ static int ls_pcie_link_up(struct dw_pcie *pci)
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return 1;
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}
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/* Forward error response of outbound non-posted requests */
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static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
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}
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static int ls_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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@@ -135,6 +145,7 @@ static int ls_pcie_host_init(struct pcie_port *pp)
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* dw_pcie_setup_rc() will reconfigure the outbound windows.
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*/
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ls_pcie_disable_outbound_atus(pcie);
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ls_pcie_fix_error_response(pcie);
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dw_pcie_dbi_ro_wr_en(pci);
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ls_pcie_clear_multifunction(pcie);
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@@ -253,6 +264,7 @@ static struct ls_pcie_drvdata ls2088_drvdata = {
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};
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static const struct of_device_id ls_pcie_of_match[] = {
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{ .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
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{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
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{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
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{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
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470
drivers/pci/dwc/pcie-histb.c
Normal file
470
drivers/pci/dwc/pcie-histb.c
Normal file
@@ -0,0 +1,470 @@
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/*
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* PCIe host controller driver for HiSilicon STB SoCs
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*
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* Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
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*
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* Authors: Ruqiang Ju <juruqiang@hisilicon.com>
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* Jianguo Sun <sunjianguo1@huawei.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/reset.h>
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#include "pcie-designware.h"
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#define to_histb_pcie(x) dev_get_drvdata((x)->dev)
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#define PCIE_SYS_CTRL0 0x0000
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#define PCIE_SYS_CTRL1 0x0004
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#define PCIE_SYS_CTRL7 0x001C
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#define PCIE_SYS_CTRL13 0x0034
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#define PCIE_SYS_CTRL15 0x003C
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#define PCIE_SYS_CTRL16 0x0040
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#define PCIE_SYS_CTRL17 0x0044
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#define PCIE_SYS_STAT0 0x0100
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#define PCIE_SYS_STAT4 0x0110
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#define PCIE_RDLH_LINK_UP BIT(5)
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#define PCIE_XMLH_LINK_UP BIT(15)
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#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
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#define PCIE_APP_LTSSM_ENABLE BIT(11)
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#define PCIE_DEVICE_TYPE_MASK GENMASK(31, 28)
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#define PCIE_WM_EP 0
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#define PCIE_WM_LEGACY BIT(1)
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#define PCIE_WM_RC BIT(30)
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#define PCIE_LTSSM_STATE_MASK GENMASK(5, 0)
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#define PCIE_LTSSM_STATE_ACTIVE 0x11
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struct histb_pcie {
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struct dw_pcie *pci;
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struct clk *aux_clk;
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struct clk *pipe_clk;
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struct clk *sys_clk;
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struct clk *bus_clk;
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struct phy *phy;
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struct reset_control *soft_reset;
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struct reset_control *sys_reset;
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struct reset_control *bus_reset;
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void __iomem *ctrl;
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int reset_gpio;
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};
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static u32 histb_pcie_readl(struct histb_pcie *histb_pcie, u32 reg)
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{
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return readl(histb_pcie->ctrl + reg);
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}
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static void histb_pcie_writel(struct histb_pcie *histb_pcie, u32 reg, u32 val)
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{
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writel(val, histb_pcie->ctrl + reg);
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}
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static void histb_pcie_dbi_w_mode(struct pcie_port *pp, bool enable)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct histb_pcie *hipcie = to_histb_pcie(pci);
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u32 val;
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val = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0);
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if (enable)
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val |= PCIE_ELBI_SLV_DBI_ENABLE;
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else
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
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histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, val);
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}
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static void histb_pcie_dbi_r_mode(struct pcie_port *pp, bool enable)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct histb_pcie *hipcie = to_histb_pcie(pci);
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u32 val;
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val = histb_pcie_readl(hipcie, PCIE_SYS_CTRL1);
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if (enable)
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val |= PCIE_ELBI_SLV_DBI_ENABLE;
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else
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
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histb_pcie_writel(hipcie, PCIE_SYS_CTRL1, val);
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}
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static u32 histb_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
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u32 reg, size_t size)
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{
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u32 val;
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histb_pcie_dbi_r_mode(&pci->pp, true);
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dw_pcie_read(base + reg, size, &val);
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histb_pcie_dbi_r_mode(&pci->pp, false);
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return val;
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}
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static void histb_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
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u32 reg, size_t size, u32 val)
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{
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histb_pcie_dbi_w_mode(&pci->pp, true);
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dw_pcie_write(base + reg, size, val);
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histb_pcie_dbi_w_mode(&pci->pp, false);
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}
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static int histb_pcie_rd_own_conf(struct pcie_port *pp, int where,
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int size, u32 *val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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int ret;
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histb_pcie_dbi_r_mode(pp, true);
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ret = dw_pcie_read(pci->dbi_base + where, size, val);
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histb_pcie_dbi_r_mode(pp, false);
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return ret;
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}
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static int histb_pcie_wr_own_conf(struct pcie_port *pp, int where,
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int size, u32 val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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int ret;
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histb_pcie_dbi_w_mode(pp, true);
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ret = dw_pcie_write(pci->dbi_base + where, size, val);
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histb_pcie_dbi_w_mode(pp, false);
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return ret;
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}
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static int histb_pcie_link_up(struct dw_pcie *pci)
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{
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struct histb_pcie *hipcie = to_histb_pcie(pci);
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u32 regval;
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u32 status;
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regval = histb_pcie_readl(hipcie, PCIE_SYS_STAT0);
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status = histb_pcie_readl(hipcie, PCIE_SYS_STAT4);
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status &= PCIE_LTSSM_STATE_MASK;
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if ((regval & PCIE_XMLH_LINK_UP) && (regval & PCIE_RDLH_LINK_UP) &&
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(status == PCIE_LTSSM_STATE_ACTIVE))
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return 1;
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return 0;
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}
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static int histb_pcie_establish_link(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct histb_pcie *hipcie = to_histb_pcie(pci);
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u32 regval;
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if (dw_pcie_link_up(pci)) {
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dev_info(pci->dev, "Link already up\n");
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return 0;
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}
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|
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/* PCIe RC work mode */
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regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0);
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regval &= ~PCIE_DEVICE_TYPE_MASK;
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regval |= PCIE_WM_RC;
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histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval);
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|
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/* setup root complex */
|
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dw_pcie_setup_rc(pp);
|
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|
||||
/* assert LTSSM enable */
|
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regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL7);
|
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regval |= PCIE_APP_LTSSM_ENABLE;
|
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histb_pcie_writel(hipcie, PCIE_SYS_CTRL7, regval);
|
||||
|
||||
return dw_pcie_wait_for_link(pci);
|
||||
}
|
||||
|
||||
static int histb_pcie_host_init(struct pcie_port *pp)
|
||||
{
|
||||
histb_pcie_establish_link(pp);
|
||||
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI))
|
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dw_pcie_msi_init(pp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct dw_pcie_host_ops histb_pcie_host_ops = {
|
||||
.rd_own_conf = histb_pcie_rd_own_conf,
|
||||
.wr_own_conf = histb_pcie_wr_own_conf,
|
||||
.host_init = histb_pcie_host_init,
|
||||
};
|
||||
|
||||
static irqreturn_t histb_pcie_msi_irq_handler(int irq, void *arg)
|
||||
{
|
||||
struct pcie_port *pp = arg;
|
||||
|
||||
return dw_handle_msi_irq(pp);
|
||||
}
|
||||
|
||||
static void histb_pcie_host_disable(struct histb_pcie *hipcie)
|
||||
{
|
||||
reset_control_assert(hipcie->soft_reset);
|
||||
reset_control_assert(hipcie->sys_reset);
|
||||
reset_control_assert(hipcie->bus_reset);
|
||||
|
||||
clk_disable_unprepare(hipcie->aux_clk);
|
||||
clk_disable_unprepare(hipcie->pipe_clk);
|
||||
clk_disable_unprepare(hipcie->sys_clk);
|
||||
clk_disable_unprepare(hipcie->bus_clk);
|
||||
|
||||
if (gpio_is_valid(hipcie->reset_gpio))
|
||||
gpio_set_value_cansleep(hipcie->reset_gpio, 0);
|
||||
}
|
||||
|
||||
static int histb_pcie_host_enable(struct pcie_port *pp)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct histb_pcie *hipcie = to_histb_pcie(pci);
|
||||
struct device *dev = pci->dev;
|
||||
int ret;
|
||||
|
||||
/* power on PCIe device if have */
|
||||
if (gpio_is_valid(hipcie->reset_gpio))
|
||||
gpio_set_value_cansleep(hipcie->reset_gpio, 1);
|
||||
|
||||
ret = clk_prepare_enable(hipcie->bus_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot prepare/enable bus clk\n");
|
||||
goto err_bus_clk;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(hipcie->sys_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot prepare/enable sys clk\n");
|
||||
goto err_sys_clk;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(hipcie->pipe_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot prepare/enable pipe clk\n");
|
||||
goto err_pipe_clk;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(hipcie->aux_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot prepare/enable aux clk\n");
|
||||
goto err_aux_clk;
|
||||
}
|
||||
|
||||
reset_control_assert(hipcie->soft_reset);
|
||||
reset_control_deassert(hipcie->soft_reset);
|
||||
|
||||
reset_control_assert(hipcie->sys_reset);
|
||||
reset_control_deassert(hipcie->sys_reset);
|
||||
|
||||
reset_control_assert(hipcie->bus_reset);
|
||||
reset_control_deassert(hipcie->bus_reset);
|
||||
|
||||
return 0;
|
||||
|
||||
err_aux_clk:
|
||||
clk_disable_unprepare(hipcie->aux_clk);
|
||||
err_pipe_clk:
|
||||
clk_disable_unprepare(hipcie->pipe_clk);
|
||||
err_sys_clk:
|
||||
clk_disable_unprepare(hipcie->sys_clk);
|
||||
err_bus_clk:
|
||||
clk_disable_unprepare(hipcie->bus_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
||||
.read_dbi = histb_pcie_read_dbi,
|
||||
.write_dbi = histb_pcie_write_dbi,
|
||||
.link_up = histb_pcie_link_up,
|
||||
};
|
||||
|
||||
static int histb_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct histb_pcie *hipcie;
|
||||
struct dw_pcie *pci;
|
||||
struct pcie_port *pp;
|
||||
struct resource *res;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device *dev = &pdev->dev;
|
||||
enum of_gpio_flags of_flags;
|
||||
unsigned long flag = GPIOF_DIR_OUT;
|
||||
int ret;
|
||||
|
||||
hipcie = devm_kzalloc(dev, sizeof(*hipcie), GFP_KERNEL);
|
||||
if (!hipcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
|
||||
if (!pci)
|
||||
return -ENOMEM;
|
||||
|
||||
hipcie->pci = pci;
|
||||
pp = &pci->pp;
|
||||
pci->dev = dev;
|
||||
pci->ops = &dw_pcie_ops;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
|
||||
hipcie->ctrl = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(hipcie->ctrl)) {
|
||||
dev_err(dev, "cannot get control reg base\n");
|
||||
return PTR_ERR(hipcie->ctrl);
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc-dbi");
|
||||
pci->dbi_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(pci->dbi_base)) {
|
||||
dev_err(dev, "cannot get rc-dbi base\n");
|
||||
return PTR_ERR(pci->dbi_base);
|
||||
}
|
||||
|
||||
hipcie->reset_gpio = of_get_named_gpio_flags(np,
|
||||
"reset-gpios", 0, &of_flags);
|
||||
if (of_flags & OF_GPIO_ACTIVE_LOW)
|
||||
flag |= GPIOF_ACTIVE_LOW;
|
||||
if (gpio_is_valid(hipcie->reset_gpio)) {
|
||||
ret = devm_gpio_request_one(dev, hipcie->reset_gpio,
|
||||
flag, "PCIe device power control");
|
||||
if (ret) {
|
||||
dev_err(dev, "unable to request gpio\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
hipcie->aux_clk = devm_clk_get(dev, "aux");
|
||||
if (IS_ERR(hipcie->aux_clk)) {
|
||||
dev_err(dev, "Failed to get PCIe aux clk\n");
|
||||
return PTR_ERR(hipcie->aux_clk);
|
||||
}
|
||||
|
||||
hipcie->pipe_clk = devm_clk_get(dev, "pipe");
|
||||
if (IS_ERR(hipcie->pipe_clk)) {
|
||||
dev_err(dev, "Failed to get PCIe pipe clk\n");
|
||||
return PTR_ERR(hipcie->pipe_clk);
|
||||
}
|
||||
|
||||
hipcie->sys_clk = devm_clk_get(dev, "sys");
|
||||
if (IS_ERR(hipcie->sys_clk)) {
|
||||
dev_err(dev, "Failed to get PCIEe sys clk\n");
|
||||
return PTR_ERR(hipcie->sys_clk);
|
||||
}
|
||||
|
||||
hipcie->bus_clk = devm_clk_get(dev, "bus");
|
||||
if (IS_ERR(hipcie->bus_clk)) {
|
||||
dev_err(dev, "Failed to get PCIe bus clk\n");
|
||||
return PTR_ERR(hipcie->bus_clk);
|
||||
}
|
||||
|
||||
hipcie->soft_reset = devm_reset_control_get(dev, "soft");
|
||||
if (IS_ERR(hipcie->soft_reset)) {
|
||||
dev_err(dev, "couldn't get soft reset\n");
|
||||
return PTR_ERR(hipcie->soft_reset);
|
||||
}
|
||||
|
||||
hipcie->sys_reset = devm_reset_control_get(dev, "sys");
|
||||
if (IS_ERR(hipcie->sys_reset)) {
|
||||
dev_err(dev, "couldn't get sys reset\n");
|
||||
return PTR_ERR(hipcie->sys_reset);
|
||||
}
|
||||
|
||||
hipcie->bus_reset = devm_reset_control_get(dev, "bus");
|
||||
if (IS_ERR(hipcie->bus_reset)) {
|
||||
dev_err(dev, "couldn't get bus reset\n");
|
||||
return PTR_ERR(hipcie->bus_reset);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
pp->msi_irq = platform_get_irq_byname(pdev, "msi");
|
||||
if (pp->msi_irq < 0) {
|
||||
dev_err(dev, "Failed to get MSI IRQ\n");
|
||||
return pp->msi_irq;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(dev, pp->msi_irq,
|
||||
histb_pcie_msi_irq_handler,
|
||||
IRQF_SHARED, "histb-pcie-msi", pp);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot request MSI IRQ\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
hipcie->phy = devm_phy_get(dev, "phy");
|
||||
if (IS_ERR(hipcie->phy)) {
|
||||
dev_info(dev, "no pcie-phy found\n");
|
||||
hipcie->phy = NULL;
|
||||
/* fall through here!
|
||||
* if no pcie-phy found, phy init
|
||||
* should be done under boot!
|
||||
*/
|
||||
} else {
|
||||
phy_init(hipcie->phy);
|
||||
}
|
||||
|
||||
pp->root_bus_nr = -1;
|
||||
pp->ops = &histb_pcie_host_ops;
|
||||
|
||||
platform_set_drvdata(pdev, hipcie);
|
||||
|
||||
ret = histb_pcie_host_enable(pp);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable host\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dw_pcie_host_init(pp);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to initialize host\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int histb_pcie_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct histb_pcie *hipcie = platform_get_drvdata(pdev);
|
||||
|
||||
histb_pcie_host_disable(hipcie);
|
||||
|
||||
if (hipcie->phy)
|
||||
phy_exit(hipcie->phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id histb_pcie_of_match[] = {
|
||||
{ .compatible = "hisilicon,hi3798cv200-pcie", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, histb_pcie_of_match);
|
||||
|
||||
static struct platform_driver histb_pcie_platform_driver = {
|
||||
.probe = histb_pcie_probe,
|
||||
.remove = histb_pcie_remove,
|
||||
.driver = {
|
||||
.name = "histb-pcie",
|
||||
.of_match_table = histb_pcie_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(histb_pcie_platform_driver);
|
||||
|
||||
MODULE_DESCRIPTION("HiSilicon STB PCIe host controller driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Reference in New Issue
Block a user