Merge tag 'pci-v4.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
- detach driver before tearing down procfs/sysfs (Alex Williamson)
- disable PCIe services during shutdown (Sinan Kaya)
- fix ASPM oops on systems with no Root Ports (Ard Biesheuvel)
- fix ASPM LTR_L1.2_THRESHOLD programming (Bjorn Helgaas)
- fix ASPM Common_Mode_Restore_Time computation (Bjorn Helgaas)
- fix portdrv MSI/MSI-X vector allocation (Dongdong Liu, Bjorn
Helgaas)
- report non-fatal AER errors only to the affected endpoint (Gabriele
Paoloni)
- distribute bus numbers, MMIO, and I/O space among hotplug bridges to
allow more devices to be hot-added (Mika Westerberg)
- fix pciehp races during initialization and surprise link down (Mika
Westerberg)
- handle surprise-removed devices in PME handling (Qiang)
- support resizable BARs for large graphics devices (Christian König)
- expose SR-IOV offset, stride, and VF device ID via sysfs (Filippo
Sironi)
- create SR-IOV virtfn/physfn sysfs links before attaching driver
(Stuart Hayes)
- fix SR-IOV "ARI Capable Hierarchy" restore issue (Tony Nguyen)
- enforce Kconfig IOV/REALLOC dependency (Sascha El-Sharkawy)
- avoid slot reset if bridge itself is broken (Jan Glauber)
- clean up pci_reset_function() path (Jan H. Schönherr)
- make pci_map_rom() fail if the option ROM is invalid (Changbin Du)
- convert timers to timer_setup() (Kees Cook)
- move PCI_QUIRKS to PCI bus Kconfig menu (Randy Dunlap)
- constify pci_dev_type and intel_mid_pci_ops (Bhumika Goyal)
- remove unnecessary pci_dev, pci_bus, resource, pcibios_set_master()
declarations (Bjorn Helgaas)
- fix endpoint framework overflows and BUG()s (Dan Carpenter)
- fix endpoint framework issues (Kishon Vijay Abraham I)
- avoid broken Cavium CN8xxx bus reset behavior (David Daney)
- extend Cavium ACS capability quirks (Vadim Lomovtsev)
- support Synopsys DesignWare RC in ECAM mode (Ard Biesheuvel)
- turn off dra7xx clocks cleanly on shutdown (Keerthy)
- fix Faraday probe error path (Wei Yongjun)
- support HiSilicon STB SoC PCIe host controller (Jianguo Sun)
- fix Hyper-V interrupt affinity issue (Dexuan Cui)
- remove useless ACPI warning for Hyper-V pass-through devices (Vitaly
Kuznetsov)
- support multiple MSI on iProc (Sandor Bodo-Merle)
- support Layerscape LS1012a and LS1046a PCIe host controllers (Hou
Zhiqiang)
- fix Layerscape default error response (Minghuan Lian)
- support MSI on Tango host controller (Marc Gonzalez)
- support Tegra186 PCIe host controller (Manikanta Maddireddy)
- use generic accessors on Tegra when possible (Thierry Reding)
- support V3 Semiconductor PCI host controller (Linus Walleij)
* tag 'pci-v4.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (85 commits)
PCI/ASPM: Add L1 Substates definitions
PCI/ASPM: Reformat ASPM register definitions
PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD
PCI/ASPM: Account for downstream device's Port Common_Mode_Restore_Time
PCI: xgene: Rename xgene_pcie_probe_bridge() to xgene_pcie_probe()
PCI: xilinx: Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up()
PCI: altera: Rename altera_pcie_link_is_up() to altera_pcie_link_up()
PCI: Fix kernel-doc build warning
PCI: Fail pci_map_rom() if the option ROM is invalid
PCI: Move pci_map_rom() error path
PCI: Move PCI_QUIRKS to the PCI bus menu
alpha/PCI: Make pdev_save_srm_config() static
PCI: Remove unused declarations
PCI: Remove redundant pci_dev, pci_bus, resource declarations
PCI: Remove redundant pcibios_set_master() declarations
PCI/PME: Handle invalid data when reading Root Status
PCI: hv: Use effective affinity mask
PCI: pciehp: Do not clear Presence Detect Changed during initialization
PCI: pciehp: Fix race condition handling surprise link down
PCI: Distribute available resources to hotplug-capable bridges
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,42 @@
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* Synopsys DesignWare PCIe root complex in ECAM shift mode
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In some cases, firmware may already have configured the Synopsys DesignWare
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PCIe controller in RC mode with static ATU window mappings that cover all
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config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion.
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In this case, there is no need for the OS to perform any low level setup
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of clocks, PHYs or device registers, nor is there any reason for the driver
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to reconfigure ATU windows for config and/or IO space accesses at runtime.
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In cases where the IP was synthesized with a minimum ATU window size of
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64 KB, it cannot be supported by the generic ECAM driver, because it
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requires special config space accessors that filter accesses to device #1
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and beyond on the first bus.
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Required properties:
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- compatible: "marvell,armada8k-pcie-ecam" or
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"socionext,synquacer-pcie-ecam" or
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"snps,dw-pcie-ecam" (must be preceded by a more specific match)
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Please refer to the binding document of "pci-host-ecam-generic" in the
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file host-generic-pci.txt for a description of the remaining required
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and optional properties.
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Example:
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pcie1: pcie@7f000000 {
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compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
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device_type = "pci";
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reg = <0x0 0x7f000000 0x0 0xf00000>;
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bus-range = <0x0 0xe>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,
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<0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
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<0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
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#interrupt-cells = <0x1>;
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interrupt-map-mask = <0x0 0x0 0x0 0x0>;
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interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>;
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msi-map = <0x0 &its 0x0 0x10000>;
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dma-coherent;
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};
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@@ -0,0 +1,68 @@
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HiSilicon STB PCIe host bridge DT description
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The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
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It shares common functions with the DesignWare PCIe core driver and inherits
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common properties defined in
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Documentation/devicetree/bindings/pci/designware-pcie.txt.
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Additional properties are described here:
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Required properties
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- compatible: Should be one of the following strings:
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"hisilicon,hi3798cv200-pcie"
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- reg: Should contain sysctl, rc_dbi, config registers location and length.
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- reg-names: Must include the following entries:
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"control": control registers of PCIe controller;
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"rc-dbi": configuration space of PCIe controller;
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"config": configuration transaction space of PCIe controller.
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- bus-range: PCI bus numbers covered.
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- interrupts: MSI interrupt.
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- interrupt-names: Must include "msi" entries.
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- clocks: List of phandle and clock specifier pairs as listed in clock-names
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property.
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- clock-name: Must include the following entries:
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"aux": auxiliary gate clock;
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"pipe": pipe gate clock;
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"sys": sys gate clock;
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"bus": bus gate clock.
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- resets: List of phandle and reset specifier pairs as listed in reset-names
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property.
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- reset-names: Must include the following entries:
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"soft": soft reset;
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"sys": sys reset;
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"bus": bus reset.
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Optional properties:
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- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
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- phys: List of phandle and phy mode specifier, should be 0.
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- phy-names: Must be "phy".
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Example:
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pcie@f9860000 {
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compatible = "hisilicon,hi3798cv200-pcie";
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reg = <0xf9860000 0x1000>,
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<0xf0000000 0x2000>,
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<0xf2000000 0x01000000>;
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reg-names = "control", "rc-dbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0 15>;
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num-lanes = <1>;
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ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
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0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg PCIE_AUX_CLK>,
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<&crg PCIE_PIPE_CLK>,
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<&crg PCIE_SYS_CLK>,
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<&crg PCIE_BUS_CLK>;
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clock-names = "aux", "pipe", "sys", "bus";
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resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
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reset-names = "soft", "sys", "bus";
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phys = <&combphy1 PHY_TYPE_PCIE>;
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phy-names = "phy";
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};
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@@ -18,6 +18,7 @@ Required properties:
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"fsl,ls2088a-pcie"
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"fsl,ls1088a-pcie"
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"fsl,ls1046a-pcie"
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"fsl,ls1012a-pcie"
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- reg: base addresses and lengths of the PCIe controller register blocks.
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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@@ -1,10 +1,15 @@
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NVIDIA Tegra PCIe controller
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Required properties:
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- compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30,
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"nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie".
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Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
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<chip> is tegra132 or tegra210.
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- compatible: Must be:
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- "nvidia,tegra20-pcie": for Tegra20
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- "nvidia,tegra30-pcie": for Tegra30
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- "nvidia,tegra124-pcie": for Tegra124 and Tegra132
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- "nvidia,tegra210-pcie": for Tegra210
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- "nvidia,tegra186-pcie": for Tegra186
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- power-domains: To ungate power partition by BPMP powergate driver. Must
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contain BPMP phandle and PCIe power partition ID. This is required only
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for Tegra186.
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- device_type: Must be "pci"
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- reg: A list of physical base address and length for each set of controller
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registers. Must contain an entry for each entry in the reg-names property.
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@@ -124,6 +129,16 @@ Power supplies for Tegra210:
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- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
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supply 1.8 V.
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Power supplies for Tegra186:
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- Required:
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- dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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- hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
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supply 1.8 V.
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- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
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Must supply 1.8 V.
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- vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
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supply 1.8 V.
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Root ports are defined as subnodes of the PCIe controller node.
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Required properties:
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@@ -546,3 +561,114 @@ Board DTS:
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status = "okay";
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};
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};
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Tegra186:
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---------
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SoC DTSI:
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pcie@10003000 {
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compatible = "nvidia,tegra186-pcie";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
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device_type = "pci";
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reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
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0x0 0x10003800 0x0 0x00000800 /* AFI registers */
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0x0 0x40000000 0x0 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
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0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
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0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
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0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
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0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
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clocks = <&bpmp TEGRA186_CLK_AFI>,
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<&bpmp TEGRA186_CLK_PCIE>,
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<&bpmp TEGRA186_CLK_PLLE>;
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clock-names = "afi", "pex", "pll_e";
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resets = <&bpmp TEGRA186_RESET_AFI>,
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<&bpmp TEGRA186_RESET_PCIE>,
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<&bpmp TEGRA186_RESET_PCIEXCLK>;
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reset-names = "afi", "pex", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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pci@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
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reg = <0x001800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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};
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Board DTS:
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pcie@10003000 {
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status = "okay";
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dvdd-pex-supply = <&vdd_pex>;
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hvdd-pex-pll-supply = <&vdd_1v8>;
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hvdd-pex-supply = <&vdd_1v8>;
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vddio-pexctl-aud-supply = <&vdd_1v8>;
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pci@1,0 {
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nvidia,num-lanes = <4>;
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status = "okay";
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};
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pci@2,0 {
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nvidia,num-lanes = <0>;
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status = "disabled";
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};
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pci@3,0 {
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nvidia,num-lanes = <1>;
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status = "disabled";
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};
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};
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@@ -60,17 +60,15 @@ Example SoC configuration:
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0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
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0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
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pci@0,1 {
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usb@1,0 {
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reg = <0x800 0 0 0 0>;
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device_type = "pci";
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phys = <&usbphy 0 0>;
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phys = <&usb0 0>;
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phy-names = "usb";
|
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};
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|
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pci@0,2 {
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usb@2,0 {
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reg = <0x1000 0 0 0 0>;
|
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device_type = "pci";
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phys = <&usbphy 0 0>;
|
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phys = <&usb0 0>;
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phy-names = "usb";
|
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};
|
||||
};
|
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|
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@@ -2,14 +2,75 @@ V3 Semiconductor V360 EPC PCI bridge
|
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|
||||
This bridge is found in the ARM Integrator/AP (Application Platform)
|
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|
||||
Integrator-specific notes:
|
||||
|
||||
- syscon: should contain a link to the syscon device node (since
|
||||
on the Integrator, some registers in the syscon are required to
|
||||
operate the V3).
|
||||
|
||||
V360 EPC specific notes:
|
||||
|
||||
- reg: should contain the base address of the V3 adapter.
|
||||
Required properties:
|
||||
- compatible: should be one of:
|
||||
"v3,v360epc-pci"
|
||||
"arm,integrator-ap-pci", "v3,v360epc-pci"
|
||||
- reg: should contain two register areas:
|
||||
first the base address of the V3 host bridge controller, 64KB
|
||||
second the configuration area register space, 16MB
|
||||
- interrupts: should contain a reference to the V3 error interrupt
|
||||
as routed on the system.
|
||||
- bus-range: see pci.txt
|
||||
- ranges: this follows the standard PCI bindings in the IEEE Std
|
||||
1275-1994 (see pci.txt) with the following restriction:
|
||||
- The non-prefetchable and prefetchable memory windows must
|
||||
each be exactly 256MB (0x10000000) in size.
|
||||
- The prefetchable memory window must be immediately adjacent
|
||||
to the non-prefetcable memory window
|
||||
- dma-ranges: three ranges for the inbound memory region. The ranges must
|
||||
be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB,
|
||||
64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked
|
||||
as pre-fetchable. Two ranges are supported by the hardware.
|
||||
|
||||
Integrator-specific required properties:
|
||||
- syscon: should contain a link to the syscon device node, since
|
||||
on the Integrator, some registers in the syscon are required to
|
||||
operate the V3 host bridge.
|
||||
|
||||
Example:
|
||||
|
||||
pci: pciv3@62000000 {
|
||||
compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
|
||||
interrupt-parent = <&pic>;
|
||||
interrupts = <17>; /* Bus error IRQ */
|
||||
clocks = <&pciclk>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
|
||||
0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
|
||||
0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
|
||||
0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
|
||||
0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
|
||||
0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
|
||||
dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
|
||||
0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
|
||||
0x02000000 0 0x80000000 /* Core module alias memory */
|
||||
0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
|
||||
interrupt-map-mask = <0xf800 0 0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 9 */
|
||||
0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
|
||||
0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
|
||||
0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
|
||||
0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
|
||||
/* IDSEL 10 */
|
||||
0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
|
||||
0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
|
||||
0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
|
||||
0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
|
||||
/* IDSEL 11 */
|
||||
0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
|
||||
0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
|
||||
0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
|
||||
0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
|
||||
/* IDSEL 12 */
|
||||
0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
|
||||
0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
|
||||
0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
|
||||
0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
|
||||
>;
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user