[POWERPC] Move PCI nodes to be sibilings with SOC nodes
Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
@@ -53,11 +53,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <00001000 f8001000 000ff000
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80000000 80000000 20000000
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e2000000 e2000000 00100000
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a0000000 a0000000 20000000
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e3000000 e3000000 00100000>;
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ranges = <00000000 f8000000 00100000>;
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reg = <f8000000 00001000>; // CCSRBAR
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bus-frequency = <0>;
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@@ -208,153 +204,6 @@
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interrupt-parent = <&mpic>;
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};
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pcie@8000 {
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <8000 1000>;
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bus-range = <0 ff>;
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ranges = <02000000 0 80000000 80000000 0 20000000
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01000000 0 00000000 e2000000 0 00100000>;
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clock-frequency = <1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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interrupt-map-mask = <fb00 0 0 0>;
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interrupt-map = <
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/* IDSEL 0x11 */
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8800 0 0 1 &i8259 9 2
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8800 0 0 2 &i8259 a 2
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8800 0 0 3 &i8259 b 2
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8800 0 0 4 &i8259 c 2
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/* IDSEL 0x12 */
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9000 0 0 1 &i8259 a 2
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9000 0 0 2 &i8259 b 2
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9000 0 0 3 &i8259 c 2
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9000 0 0 4 &i8259 9 2
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// IDSEL 0x1c USB
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e000 0 0 0 &i8259 c 2
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e100 0 0 0 &i8259 9 2
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e200 0 0 0 &i8259 a 2
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e300 0 0 0 &i8259 b 2
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// IDSEL 0x1d Audio
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e800 0 0 0 &i8259 6 2
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// IDSEL 0x1e Legacy
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f000 0 0 0 &i8259 7 2
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f100 0 0 0 &i8259 7 2
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// IDSEL 0x1f IDE/SATA
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f800 0 0 0 &i8259 e 2
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f900 0 0 0 &i8259 5 2
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>;
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uli1575@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <02000000 0 80000000
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02000000 0 80000000
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0 20000000
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01000000 0 00000000
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01000000 0 00000000
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0 00100000>;
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pci_bridge@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <02000000 0 80000000
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02000000 0 80000000
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0 20000000
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01000000 0 00000000
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01000000 0 00000000
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0 00100000>;
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isa@1e {
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device_type = "isa";
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#interrupt-cells = <2>;
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <f000 0 0 0 0>;
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ranges = <1 0 01000000 0 0
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00001000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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reg = <1 20 2
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1 a0 2
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1 4d0 2>;
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interrupt-controller;
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device_type = "interrupt-controller";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <9 2>;
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interrupt-parent =
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<&mpic>;
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};
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i8042@60 {
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#size-cells = <0>;
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#address-cells = <1>;
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reg = <1 60 1 1 64 1>;
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interrupts = <1 3 c 3>;
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interrupt-parent =
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<&i8259>;
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keyboard@0 {
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reg = <0>;
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compatible = "pnpPNP,303";
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};
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mouse@1 {
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reg = <1>;
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compatible = "pnpPNP,f03";
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};
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};
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rtc@70 {
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compatible =
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"pnpPNP,b00";
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reg = <1 70 2>;
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};
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gpio@400 {
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reg = <1 400 80>;
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};
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};
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};
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};
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};
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pcie@9000 {
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <9000 1000>;
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bus-range = <0 ff>;
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ranges = <02000000 0 a0000000 a0000000 0 20000000
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01000000 0 00000000 e3000000 0 00100000>;
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clock-frequency = <1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <19 2>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 4 1
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0000 0 0 2 &mpic 5 1
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0000 0 0 3 &mpic 6 1
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0000 0 0 4 &mpic 7 1
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>;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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@@ -366,4 +215,164 @@
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big-endian;
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};
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};
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pcie@f8008000 {
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <f8008000 1000>;
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bus-range = <0 ff>;
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ranges = <02000000 0 80000000 80000000 0 20000000
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01000000 0 00000000 e2000000 0 00100000>;
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clock-frequency = <1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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interrupt-map-mask = <fb00 0 0 0>;
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interrupt-map = <
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/* IDSEL 0x11 */
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8800 0 0 1 &i8259 9 2
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8800 0 0 2 &i8259 a 2
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8800 0 0 3 &i8259 b 2
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8800 0 0 4 &i8259 c 2
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/* IDSEL 0x12 */
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9000 0 0 1 &i8259 a 2
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9000 0 0 2 &i8259 b 2
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9000 0 0 3 &i8259 c 2
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9000 0 0 4 &i8259 9 2
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// IDSEL 0x1c USB
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e000 0 0 0 &i8259 c 2
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e100 0 0 0 &i8259 9 2
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e200 0 0 0 &i8259 a 2
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e300 0 0 0 &i8259 b 2
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// IDSEL 0x1d Audio
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e800 0 0 0 &i8259 6 2
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// IDSEL 0x1e Legacy
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f000 0 0 0 &i8259 7 2
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f100 0 0 0 &i8259 7 2
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// IDSEL 0x1f IDE/SATA
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f800 0 0 0 &i8259 e 2
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f900 0 0 0 &i8259 5 2
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <02000000 0 80000000
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02000000 0 80000000
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0 20000000
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01000000 0 00000000
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01000000 0 00000000
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0 00100000>;
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uli1575@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <02000000 0 80000000
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02000000 0 80000000
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0 20000000
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01000000 0 00000000
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01000000 0 00000000
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0 00100000>;
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isa@1e {
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device_type = "isa";
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#interrupt-cells = <2>;
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <f000 0 0 0 0>;
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ranges = <1 0 01000000 0 0
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00001000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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reg = <1 20 2
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1 a0 2
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1 4d0 2>;
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interrupt-controller;
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device_type = "interrupt-controller";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <9 2>;
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interrupt-parent = <&mpic>;
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};
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i8042@60 {
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#size-cells = <0>;
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#address-cells = <1>;
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reg = <1 60 1 1 64 1>;
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interrupts = <1 3 c 3>;
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interrupt-parent =
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<&i8259>;
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keyboard@0 {
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reg = <0>;
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compatible = "pnpPNP,303";
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};
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mouse@1 {
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reg = <1>;
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compatible = "pnpPNP,f03";
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};
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};
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rtc@70 {
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compatible =
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"pnpPNP,b00";
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reg = <1 70 2>;
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};
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gpio@400 {
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reg = <1 400 80>;
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};
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};
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};
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};
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};
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pcie@f8009000 {
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <f8009000 1000>;
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bus-range = <0 ff>;
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ranges = <02000000 0 a0000000 a0000000 0 20000000
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01000000 0 00000000 e3000000 0 00100000>;
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clock-frequency = <1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <19 2>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 4 1
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0000 0 0 2 &mpic 5 1
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0000 0 0 3 &mpic 6 1
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0000 0 0 4 &mpic 7 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <02000000 0 a0000000
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02000000 0 a0000000
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0 20000000
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01000000 0 00000000
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01000000 0 00000000
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0 00100000>;
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};
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};
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};
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