[POWERPC] Move PCI nodes to be sibilings with SOC nodes
Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
@@ -42,13 +42,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <00001000 e0001000 000ff000
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80000000 80000000 10000000
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e2000000 e2000000 00800000
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90000000 90000000 10000000
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e2800000 e2800000 00800000
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a0000000 a0000000 20000000
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e3000000 e3000000 01000000>;
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ranges = <00000000 e0000000 00100000>;
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reg = <e0000000 00001000>; // CCSRBAR
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bus-frequency = <0>;
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@@ -187,203 +181,6 @@
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fsl,has-rstcr;
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};
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pci@8000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x4 (PCIX Slot 2) */
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02000 0 0 1 &mpic 0 1
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02000 0 0 2 &mpic 1 1
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02000 0 0 3 &mpic 2 1
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02000 0 0 4 &mpic 3 1
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/* IDSEL 0x5 (PCIX Slot 3) */
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02800 0 0 1 &mpic 1 1
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02800 0 0 2 &mpic 2 1
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02800 0 0 3 &mpic 3 1
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02800 0 0 4 &mpic 0 1
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/* IDSEL 0x6 (PCIX Slot 4) */
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03000 0 0 1 &mpic 2 1
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03000 0 0 2 &mpic 3 1
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03000 0 0 3 &mpic 0 1
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03000 0 0 4 &mpic 1 1
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/* IDSEL 0x8 (PCIX Slot 5) */
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04000 0 0 1 &mpic 0 1
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04000 0 0 2 &mpic 1 1
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04000 0 0 3 &mpic 2 1
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04000 0 0 4 &mpic 3 1
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/* IDSEL 0xC (Tsi310 bridge) */
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06000 0 0 1 &mpic 0 1
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06000 0 0 2 &mpic 1 1
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06000 0 0 3 &mpic 2 1
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06000 0 0 4 &mpic 3 1
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/* IDSEL 0x14 (Slot 2) */
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0a000 0 0 1 &mpic 0 1
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0a000 0 0 2 &mpic 1 1
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0a000 0 0 3 &mpic 2 1
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0a000 0 0 4 &mpic 3 1
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/* IDSEL 0x15 (Slot 3) */
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0a800 0 0 1 &mpic 1 1
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0a800 0 0 2 &mpic 2 1
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0a800 0 0 3 &mpic 3 1
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0a800 0 0 4 &mpic 0 1
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/* IDSEL 0x16 (Slot 4) */
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0b000 0 0 1 &mpic 2 1
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0b000 0 0 2 &mpic 3 1
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0b000 0 0 3 &mpic 0 1
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0b000 0 0 4 &mpic 1 1
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/* IDSEL 0x18 (Slot 5) */
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0c000 0 0 1 &mpic 0 1
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0c000 0 0 2 &mpic 1 1
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0c000 0 0 3 &mpic 2 1
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0c000 0 0 4 &mpic 3 1
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/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
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0E000 0 0 1 &mpic 0 1
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0E000 0 0 2 &mpic 1 1
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0E000 0 0 3 &mpic 2 1
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0E000 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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bus-range = <0 0>;
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ranges = <02000000 0 80000000 80000000 0 10000000
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01000000 0 00000000 e2000000 0 00800000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <8000 1000>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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pci_bridge@1c {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x00 (PrPMC Site) */
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0000 0 0 1 &mpic 0 1
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0000 0 0 2 &mpic 1 1
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0000 0 0 3 &mpic 2 1
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0000 0 0 4 &mpic 3 1
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/* IDSEL 0x04 (VIA chip) */
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2000 0 0 1 &mpic 0 1
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2000 0 0 2 &mpic 1 1
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2000 0 0 3 &mpic 2 1
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2000 0 0 4 &mpic 3 1
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/* IDSEL 0x05 (8139) */
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2800 0 0 1 &mpic 1 1
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/* IDSEL 0x06 (Slot 6) */
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3000 0 0 1 &mpic 2 1
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3000 0 0 2 &mpic 3 1
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3000 0 0 3 &mpic 0 1
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3000 0 0 4 &mpic 1 1
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/* IDESL 0x07 (Slot 7) */
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3800 0 0 1 &mpic 3 1
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3800 0 0 2 &mpic 0 1
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3800 0 0 3 &mpic 1 1
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3800 0 0 4 &mpic 2 1>;
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reg = <e000 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <02000000 0 80000000
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02000000 0 80000000
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0 20000000
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01000000 0 00000000
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01000000 0 00000000
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0 00080000>;
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clock-frequency = <1fca055>;
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isa@4 {
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device_type = "isa";
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#interrupt-cells = <2>;
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <2000 0 0 0 0>;
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ranges = <1 0 01000000 0 0 00001000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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interrupt-controller;
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device_type = "interrupt-controller";
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reg = <1 20 2
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1 a0 2
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1 4d0 2>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <0 1>;
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interrupt-parent = <&mpic>;
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};
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rtc@70 {
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compatible = "pnpPNP,b00";
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reg = <1 70 2>;
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};
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};
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};
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};
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pci@9000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x15 */
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a800 0 0 1 &mpic b 1
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a800 0 0 2 &mpic 1 1
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a800 0 0 3 &mpic 2 1
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a800 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <19 2>;
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bus-range = <0 0>;
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ranges = <02000000 0 90000000 90000000 0 10000000
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01000000 0 00000000 e2800000 0 00800000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <9000 1000>;
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compatible = "fsl,mpc8540-pci";
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device_type = "pci";
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};
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/* PCI Express */
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pcie@a000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 (PEX) */
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00000 0 0 1 &mpic 0 1
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00000 0 0 2 &mpic 1 1
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00000 0 0 3 &mpic 2 1
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00000 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <1a 2>;
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bus-range = <0 ff>;
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ranges = <02000000 0 a0000000 a0000000 0 20000000
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01000000 0 00000000 e3000000 0 08000000>;
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clock-frequency = <1fca055>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <a000 1000>;
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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@@ -395,4 +192,214 @@
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big-endian;
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};
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};
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pci@e0008000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x4 (PCIX Slot 2) */
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02000 0 0 1 &mpic 0 1
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02000 0 0 2 &mpic 1 1
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02000 0 0 3 &mpic 2 1
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02000 0 0 4 &mpic 3 1
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/* IDSEL 0x5 (PCIX Slot 3) */
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02800 0 0 1 &mpic 1 1
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02800 0 0 2 &mpic 2 1
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02800 0 0 3 &mpic 3 1
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02800 0 0 4 &mpic 0 1
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/* IDSEL 0x6 (PCIX Slot 4) */
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03000 0 0 1 &mpic 2 1
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03000 0 0 2 &mpic 3 1
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03000 0 0 3 &mpic 0 1
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03000 0 0 4 &mpic 1 1
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/* IDSEL 0x8 (PCIX Slot 5) */
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04000 0 0 1 &mpic 0 1
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04000 0 0 2 &mpic 1 1
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04000 0 0 3 &mpic 2 1
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04000 0 0 4 &mpic 3 1
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/* IDSEL 0xC (Tsi310 bridge) */
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06000 0 0 1 &mpic 0 1
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06000 0 0 2 &mpic 1 1
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06000 0 0 3 &mpic 2 1
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06000 0 0 4 &mpic 3 1
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/* IDSEL 0x14 (Slot 2) */
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0a000 0 0 1 &mpic 0 1
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0a000 0 0 2 &mpic 1 1
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0a000 0 0 3 &mpic 2 1
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0a000 0 0 4 &mpic 3 1
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/* IDSEL 0x15 (Slot 3) */
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0a800 0 0 1 &mpic 1 1
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0a800 0 0 2 &mpic 2 1
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0a800 0 0 3 &mpic 3 1
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0a800 0 0 4 &mpic 0 1
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/* IDSEL 0x16 (Slot 4) */
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0b000 0 0 1 &mpic 2 1
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0b000 0 0 2 &mpic 3 1
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0b000 0 0 3 &mpic 0 1
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0b000 0 0 4 &mpic 1 1
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/* IDSEL 0x18 (Slot 5) */
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0c000 0 0 1 &mpic 0 1
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0c000 0 0 2 &mpic 1 1
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0c000 0 0 3 &mpic 2 1
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0c000 0 0 4 &mpic 3 1
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/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
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0E000 0 0 1 &mpic 0 1
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0E000 0 0 2 &mpic 1 1
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0E000 0 0 3 &mpic 2 1
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0E000 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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bus-range = <0 0>;
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ranges = <02000000 0 80000000 80000000 0 10000000
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01000000 0 00000000 e2000000 0 00800000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008000 1000>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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pci_bridge@1c {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x00 (PrPMC Site) */
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0000 0 0 1 &mpic 0 1
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0000 0 0 2 &mpic 1 1
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0000 0 0 3 &mpic 2 1
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0000 0 0 4 &mpic 3 1
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/* IDSEL 0x04 (VIA chip) */
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2000 0 0 1 &mpic 0 1
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2000 0 0 2 &mpic 1 1
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2000 0 0 3 &mpic 2 1
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2000 0 0 4 &mpic 3 1
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/* IDSEL 0x05 (8139) */
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2800 0 0 1 &mpic 1 1
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/* IDSEL 0x06 (Slot 6) */
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3000 0 0 1 &mpic 2 1
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3000 0 0 2 &mpic 3 1
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3000 0 0 3 &mpic 0 1
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3000 0 0 4 &mpic 1 1
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/* IDESL 0x07 (Slot 7) */
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3800 0 0 1 &mpic 3 1
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3800 0 0 2 &mpic 0 1
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3800 0 0 3 &mpic 1 1
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3800 0 0 4 &mpic 2 1>;
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reg = <e000 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <02000000 0 80000000
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02000000 0 80000000
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0 20000000
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01000000 0 00000000
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01000000 0 00000000
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0 00080000>;
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clock-frequency = <1fca055>;
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isa@4 {
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device_type = "isa";
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#interrupt-cells = <2>;
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <2000 0 0 0 0>;
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ranges = <1 0 01000000 0 0 00001000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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interrupt-controller;
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device_type = "interrupt-controller";
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reg = <1 20 2
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1 a0 2
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1 4d0 2>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <0 1>;
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interrupt-parent = <&mpic>;
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};
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rtc@70 {
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compatible = "pnpPNP,b00";
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reg = <1 70 2>;
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};
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};
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};
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};
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pci@e0009000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x15 */
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a800 0 0 1 &mpic b 1
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a800 0 0 2 &mpic 1 1
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a800 0 0 3 &mpic 2 1
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a800 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <19 2>;
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bus-range = <0 0>;
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ranges = <02000000 0 90000000 90000000 0 10000000
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01000000 0 00000000 e2800000 0 00800000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0009000 1000>;
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compatible = "fsl,mpc8540-pci";
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device_type = "pci";
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};
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pcie@e000a000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 (PEX) */
|
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00000 0 0 1 &mpic 0 1
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00000 0 0 2 &mpic 1 1
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00000 0 0 3 &mpic 2 1
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00000 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <1a 2>;
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bus-range = <0 ff>;
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ranges = <02000000 0 a0000000 a0000000 0 20000000
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01000000 0 00000000 e3000000 0 08000000>;
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clock-frequency = <1fca055>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e000a000 1000>;
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <02000000 0 a0000000
|
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02000000 0 a0000000
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0 20000000
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01000000 0 00000000
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01000000 0 00000000
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0 08000000>;
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};
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||||
};
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||||
};
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|
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