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drm/amd/powerplay: improve OD code robustness

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add protection code to avoid lower frequency trigger over drive.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Tianci Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
tianci yin
2018-12-04 16:07:18 +08:00
committed by Alex Deucher
parent 4944af670b
commit 1b3b27b2a1
2 changed files with 16 additions and 8 deletions
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4
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
View File

@@ -3589,8 +3589,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
} }
if (i >= sclk_table->count) { if (i >= sclk_table->count) {
if (sclk > sclk_table->dpm_levels[i-1].value) {
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
sclk_table->dpm_levels[i-1].value = sclk; sclk_table->dpm_levels[i-1].value = sclk;
}
} else { } else {
/* TODO: Check SCLK in DAL's minimum clocks /* TODO: Check SCLK in DAL's minimum clocks
* in case DeepSleep divider update is required. * in case DeepSleep divider update is required.
@@ -3607,9 +3609,11 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
} }
if (i >= mclk_table->count) { if (i >= mclk_table->count) {
if (mclk > mclk_table->dpm_levels[i-1].value) {
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
mclk_table->dpm_levels[i-1].value = mclk; mclk_table->dpm_levels[i-1].value = mclk;
} }
}
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;

4
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
View File

@@ -3266,9 +3266,11 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
} }
if (i >= sclk_table->count) { if (i >= sclk_table->count) {
if (sclk > sclk_table->dpm_levels[i-1].value) {
data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
sclk_table->dpm_levels[i-1].value = sclk; sclk_table->dpm_levels[i-1].value = sclk;
} }
}
for (i = 0; i < mclk_table->count; i++) { for (i = 0; i < mclk_table->count; i++) {
if (mclk == mclk_table->dpm_levels[i].value) if (mclk == mclk_table->dpm_levels[i].value)
@@ -3276,9 +3278,11 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
} }
if (i >= mclk_table->count) { if (i >= mclk_table->count) {
if (mclk > mclk_table->dpm_levels[i-1].value) {
data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
mclk_table->dpm_levels[i-1].value = mclk; mclk_table->dpm_levels[i-1].value = mclk;
} }
}
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK; data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;