xiaomi-sm8450/android_kernel_xiaomi_sm8450
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Merge branches 'clk-spdx', 'clk-qcom-dfs', 'clk-smp2s11-include', 'clk-qcom-8996-missing' and 'clk-qcom-qspi' into clk-next

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- Tag various drivers with SPDX license tags
  - Support dynamic frequency switching (DFS) on qcom SDM845 GCC
  - Only use s2mps11 dt-binding defines instead of redefining them in the driver
  - Add some more missing clks to qcom MSM8996 GCC
  - Quad SPI clks on qcom SDM845

* clk-spdx:
  clk: mvebu: use SPDX-License-Identifier
  clk: renesas: Convert to SPDX identifiers
  clk: renesas: use SPDX identifier for Renesas drivers
  clk: s2mps11,s3c64xx: Add SPDX license identifiers
  clk: max77686: Add SPDX license identifiers

* clk-qcom-dfs:
  clk: qcom: Allocate space for NULL terimation in DFS table
  clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845
  clk: qcom: Add support for RCG to register for DFS

* clk-smp2s11-include:
  clk: s2mps11: Use existing defines from bindings for clock IDs

* clk-qcom-8996-missing:
  clk: qcom: Add some missing gcc clks for msm8996

* clk-qcom-qspi:
  clk: qcom: Add qspi (Quad SPI) clocks for sdm845
  clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
This commit is contained in:
Stephen Boyd
2018-10-18 15:33:28 -07:00
parent c3828949a2 2bdb2a1cca 8748b4a786 b567752144 4f83d9b848
commit 1affdc35e0
7 changed files with 580 additions and 102 deletions
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9
include/dt-bindings/clock/qcom,gcc-msm8996.h
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@@ -235,6 +235,15 @@
#define GCC_RX1_USB2_CLKREF_CLK 218
#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219
#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220
#define GCC_EDP_CLKREF_CLK 221
#define GCC_MSS_CFG_AHB_CLK 222
#define GCC_MSS_Q6_BIMC_AXI_CLK 223
#define GCC_MSS_SNOC_AXI_CLK 224
#define GCC_MSS_MNOC_BIMC_AXI_CLK 225
#define GCC_DCC_AHB_CLK 226
#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227
#define GCC_MMSS_GPLL0_DIV_CLK 228
#define GCC_MSS_GPLL0_DIV_CLK 229
#define GCC_SYSTEM_NOC_BCR 0
#define GCC_CONFIG_NOC_BCR 1

3
include/dt-bindings/clock/qcom,gcc-sdm845.h
View File

@@ -194,6 +194,9 @@
#define GPLL4 184
#define GCC_CPUSS_DVM_BUS_CLK 185
#define GCC_CPUSS_GNOC_CLK 186
#define GCC_QSPI_CORE_CLK_SRC 187
#define GCC_QSPI_CORE_CLK 188
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
/* GCC Resets */
#define GCC_MMSS_BCR 0