sh_eth: rename EESIPR bits
Since the commit b0ca2a21f7
("sh_eth: Add support of SH7763 to sh_eth")
the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with
the *enum* declaring the EESR bits (interrupt status) WRT bit naming and
formatting. I'd like to restore the consistency by using EESIPR as the bit
name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the
bits according to the available Renesas SH77{34|63} manuals; additionally,
reconstruct couple names using the EESR bit declaration above...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:

committed by
David S. Miller

parent
63c1904290
commit
1a0bee6c1e
@@ -556,7 +556,7 @@ static struct sh_eth_cpu_data r8a7740_data = {
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.ecsr_value = ECSR_ICD | ECSR_MPD,
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.ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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.eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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@@ -702,7 +702,7 @@ static struct sh_eth_cpu_data sh7757_data = {
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.register_type = SH_ETH_REG_FAST_SH4,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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.eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
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.tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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.eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
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@@ -769,7 +769,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
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.ecsr_value = ECSR_ICD | ECSR_MPD,
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.ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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.eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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@@ -800,7 +800,7 @@ static struct sh_eth_cpu_data sh7734_data = {
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.ecsr_value = ECSR_ICD | ECSR_MPD,
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.ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
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.eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff,
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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@@ -830,7 +830,7 @@ static struct sh_eth_cpu_data sh7763_data = {
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.ecsr_value = ECSR_ICD | ECSR_MPD,
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.ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
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.eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff,
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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@@ -851,7 +851,7 @@ static struct sh_eth_cpu_data sh7763_data = {
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static struct sh_eth_cpu_data sh7619_data = {
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.register_type = SH_ETH_REG_FAST_SH3_SH2,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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.eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
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.apr = 1,
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.mpr = 1,
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@@ -862,7 +862,7 @@ static struct sh_eth_cpu_data sh7619_data = {
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static struct sh_eth_cpu_data sh771x_data = {
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.register_type = SH_ETH_REG_FAST_SH3_SH2,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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.eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
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.tsu = 1,
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};
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@@ -1547,10 +1547,10 @@ static void sh_eth_emac_interrupt(struct net_device *ndev)
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sh_eth_rcv_snd_disable(ndev);
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} else {
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/* Link Up */
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sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
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sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
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/* clear int */
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sh_eth_modify(ndev, ECSR, 0, 0);
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sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, DMAC_M_ECI);
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sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
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/* enable tx and rx */
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sh_eth_rcv_snd_enable(ndev);
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}
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@@ -1652,7 +1652,7 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
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* bit...
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*/
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intr_enable = sh_eth_read(ndev, EESIPR);
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intr_status &= intr_enable | DMAC_M_ECI;
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intr_status &= intr_enable | EESIPR_ECIIP;
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if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
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cd->eesr_err_check))
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ret = IRQ_HANDLED;
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@@ -3199,7 +3199,7 @@ static int sh_eth_wol_setup(struct net_device *ndev)
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/* Only allow ECI interrupts */
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synchronize_irq(ndev->irq);
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napi_disable(&mdp->napi);
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sh_eth_write(ndev, DMAC_M_ECI, EESIPR);
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sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
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/* Enable MagicPacket */
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sh_eth_modify(ndev, ECMR, 0, ECMR_MPDE);
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