idle, x86: Allow off-lined CPU to enter deeper C states
Currently when a CPU is off-lined it enters either MWAIT-based idle or, if MWAIT is not desired or supported, HLT-based idle (which places the processor in C1 state). This patch allows processors without MWAIT support to stay in states deeper than C1. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com> Signed-off-by: Len Brown <len.brown@intel.com>
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Len Brown

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e07510585a
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1a022e3f1b
@@ -71,6 +71,34 @@ typedef int (*cpuidle_enter_t)(struct cpuidle_device *dev,
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static cpuidle_enter_t cpuidle_enter_ops;
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/**
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* cpuidle_play_dead - cpu off-lining
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*
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* Only returns in case of an error
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*/
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int cpuidle_play_dead(void)
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{
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struct cpuidle_device *dev = __this_cpu_read(cpuidle_devices);
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struct cpuidle_driver *drv = cpuidle_get_driver();
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int i, dead_state = -1;
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int power_usage = -1;
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/* Find lowest-power state that supports long-term idle */
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for (i = CPUIDLE_DRIVER_STATE_START; i < drv->state_count; i++) {
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struct cpuidle_state *s = &drv->states[i];
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if (s->power_usage < power_usage && s->enter_dead) {
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power_usage = s->power_usage;
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dead_state = i;
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}
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}
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if (dead_state != -1)
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return drv->states[dead_state].enter_dead(dev, dead_state);
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return -ENODEV;
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}
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/**
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* cpuidle_idle_call - the main idle loop
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*
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