Add TI CDCE925 I2C controlled clock synthesizer driver
This driver supports the TI CDCE925 programmable clock synthesizer. The chip contains two PLLs with spread-spectrum clocking support and five output dividers. The driver only supports the following setup, and uses a fixed setting for the output muxes: Y1 is derived from the input clock Y2 and Y3 derive from PLL1 Y4 and Y5 derive from PLL2 Given a target output frequency, the driver will set the PLL and divider to best approximate the desired output. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Šī revīzija ir iekļauta:

revīziju iesūtīja
Michael Turquette

vecāks
4d52b2acef
revīzija
19fbbbbcd3
@@ -78,6 +78,23 @@ config COMMON_CLK_SI570
|
||||
This driver supports Silicon Labs 570/571/598/599 programmable
|
||||
clock generators.
|
||||
|
||||
config COMMON_CLK_CDCE925
|
||||
tristate "Clock driver for TI CDCE925 devices"
|
||||
depends on I2C
|
||||
depends on OF
|
||||
select REGMAP_I2C
|
||||
help
|
||||
---help---
|
||||
This driver supports the TI CDCE925 programmable clock synthesizer.
|
||||
The chip contains two PLLs with spread-spectrum clocking support and
|
||||
five output dividers. The driver only supports the following setup,
|
||||
and uses a fixed setting for the output muxes.
|
||||
Y1 is derived from the input clock
|
||||
Y2 and Y3 derive from PLL1
|
||||
Y4 and Y5 derive from PLL2
|
||||
Given a target output frequency, the driver will set the PLL and
|
||||
divider to best approximate the desired output.
|
||||
|
||||
config COMMON_CLK_S2MPS11
|
||||
tristate "Clock driver for S2MPS1X/S5M8767 MFD"
|
||||
depends on MFD_SEC_CORE
|
||||
|
Atsaukties uz šo jaunā problēmā
Block a user