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xtensa: fix a7 clobbering in coprocessor context load/store

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commit 839769c35477d4acc2369e45000ca7b0b6af39a7 upstream.

Fast coprocessor exception handler saves a3..a6, but coprocessor context
load/store code uses a4..a7 as temporaries, potentially clobbering a7.
'Potentially' because coprocessor state load/store macros may not use
all four temporary registers (and neither FPU nor HiFi macros do).
Use a3..a6 as intended.

Cc: stable@vger.kernel.org
Fixes: c658eac628 ("[XTENSA] Add support for configurable registers and coprocessors")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Max Filippov
2022-04-13 22:44:36 -07:00
committed by Greg Kroah-Hartman
parent f399ab11dd
commit 19f6dcb1f0
1 changed files with 2 additions and 2 deletions
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4
arch/xtensa/kernel/coprocessor.S
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@@ -29,7 +29,7 @@
.if XTENSA_HAVE_COPROCESSOR(x); \ .if XTENSA_HAVE_COPROCESSOR(x); \
.align 4; \ .align 4; \
.Lsave_cp_regs_cp##x: \ .Lsave_cp_regs_cp##x: \
xchal_cp##x##_store a2 a4 a5 a6 a7; \ xchal_cp##x##_store a2 a3 a4 a5 a6; \
jx a0; \ jx a0; \
.endif .endif
@@ -46,7 +46,7 @@
.if XTENSA_HAVE_COPROCESSOR(x); \ .if XTENSA_HAVE_COPROCESSOR(x); \
.align 4; \ .align 4; \
.Lload_cp_regs_cp##x: \ .Lload_cp_regs_cp##x: \
xchal_cp##x##_load a2 a4 a5 a6 a7; \ xchal_cp##x##_load a2 a3 a4 a5 a6; \
jx a0; \ jx a0; \
.endif .endif