Merge fc8070a9c5
("arm64: Add Neoverse-N2, Cortex-A710 CPU part definition") into android-mainline
Steps on the way to 5.10.105 Resolves conflicts in: arch/arm64/include/asm/cputype.h Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: Ic3c4e967837b69a70cbfd11ab6940fc63e670a28
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@@ -59,6 +59,7 @@
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#define ARM_CPU_IMP_NVIDIA 0x4E
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#define ARM_CPU_IMP_FUJITSU 0x46
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#define ARM_CPU_IMP_HISI 0x48
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#define ARM_CPU_IMP_APPLE 0x61
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#define ARM_CPU_PART_AEM_V8 0xD0F
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#define ARM_CPU_PART_FOUNDATION 0xD00
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@@ -102,6 +103,9 @@
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#define HISI_CPU_PART_TSV110 0xD01
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#define APPLE_CPU_PART_M1_ICESTORM 0x022
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#define APPLE_CPU_PART_M1_FIRESTORM 0x023
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#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
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#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
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#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
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@@ -133,6 +137,8 @@
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#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
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#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
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#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
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#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
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#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
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/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
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#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
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