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Merge tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

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Cleanups for the Samsung platforms

Various cleanup changes that the device driver changes are built upon.
Since the samsung cleanups depend on the device tree series, which
depends on the first set of cleanups for tegra.

* tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: EXYNOS: Use gpio_request_one
  ARM: S5PV210: Use gpio_request_one
  ARM: S3C64XX: Modified according to SPI consolidation work
  ARM: S5PV210: Modified files for SPI consolidation work
  ARM: S5P64X0: Modified files for SPI consolidation work
  ARM: S5PC100: Modified files for SPI consolidation work
  ARM: S3C64XX: Modified files for SPI consolidation work
  ARM: SAMSUNG: Consolidation of SPI platform devices to plat-samsung
  ARM: SAMSUNG: Remove SPI bus clocks from platform data
  ARM: S5PV210: Add SPI clkdev support
  ARM: S5P64X0: Add SPI clkdev support
  ARM: S5PC100: Add SPI clkdev support
  ARM: S3C64XX: Add SPI clkdev support
  spi/s3c64xx: Use bus clocks created using clkdev
  mmc: sdhci-s3c: Use generic clock names for sdhci bus clock options
  ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names
  ARM: SAMSUNG: Remove SDHCI bus clocks from platform data
  ARM: SAMSUNG: Use kmemdup rather than duplicating its implementation
  ARM: EXYNOS: remove exynos4_scu_enable()
This commit is contained in:
Linus Torvalds
2012-01-09 14:30:28 -08:00
부모 dfc1ebe766 b48741cce3
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24
arch/arm/mach-exynos/pm.c
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@@ -23,6 +23,7 @@
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/smp_scu.h>
#include <plat/cpu.h>
#include <plat/pm.h>
@@ -213,27 +214,6 @@ static int exynos4_pm_add(struct device *dev)
return 0;
}
/* This function copy from linux/arch/arm/kernel/smp_scu.c */
void exynos4_scu_enable(void __iomem *scu_base)
{
u32 scu_ctrl;
scu_ctrl = __raw_readl(scu_base);
/* already enabled? */
if (scu_ctrl & 1)
return;
scu_ctrl |= 1;
__raw_writel(scu_ctrl, scu_base);
/*
* Ensure that the data accessed by CPU0 before the SCU was
* initialised is visible to the other CPUs.
*/
flush_cache_all();
}
static unsigned long pll_base_rate;
static void exynos4_restore_pll(void)
@@ -404,7 +384,7 @@ static void exynos4_pm_resume(void)
exynos4_restore_pll();
exynos4_scu_enable(S5P_VA_SCU);
scu_enable(S5P_VA_SCU);
#ifdef CONFIG_CACHE_L2X0
s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));