Merge tag 'iommu-updates-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel: - PASID table handling updates for the Intel VT-d driver. It implements a global PASID space now so that applications usings multiple devices will just have one PASID. - A new config option to make iommu passthroug mode the default. - New sysfs attribute for iommu groups to export the type of the default domain. - A debugfs interface (for debug only) usable by IOMMU drivers to export internals to user-space. - R-Car Gen3 SoCs support for the ipmmu-vmsa driver - The ARM-SMMU now aborts transactions from unknown devices and devices not attached to any domain. - Various cleanups and smaller fixes all over the place. * tag 'iommu-updates-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (42 commits) iommu/omap: Fix cache flushes on L2 table entries iommu: Remove the ->map_sg indirection iommu/arm-smmu-v3: Abort all transactions if SMMU is enabled in kdump kernel iommu/arm-smmu-v3: Prevent any devices access to memory without registration iommu/ipmmu-vmsa: Don't register as BUS IOMMU if machine doesn't have IPMMU-VMSA iommu/ipmmu-vmsa: Clarify supported platforms iommu/ipmmu-vmsa: Fix allocation in atomic context iommu: Add config option to set passthrough as default iommu: Add sysfs attribyte for domain type iommu/arm-smmu-v3: sync the OVACKFLG to PRIQ consumer register iommu/arm-smmu: Error out only if not enough context interrupts iommu/io-pgtable-arm-v7s: Abort allocation when table address overflows the PTE iommu/io-pgtable-arm: Fix pgtable allocation in selftest iommu/vt-d: Remove the obsolete per iommu pasid tables iommu/vt-d: Apply per pci device pasid table in SVA iommu/vt-d: Allocate and free pasid table iommu/vt-d: Per PCI device pasid table interfaces iommu/vt-d: Add for_each_device_domain() helper iommu/vt-d: Move device_domain_info to header iommu/vt-d: Apply global PASID in SVA ...
This commit is contained in:
Linus Torvalds
@@ -265,11 +265,6 @@ static inline void dmar_copy_shared_irte(struct irte *dst, struct irte *src)
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#define PDA_LOW_BIT 26
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#define PDA_HIGH_BIT 32
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enum {
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IRQ_REMAP_XAPIC_MODE,
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IRQ_REMAP_X2APIC_MODE,
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};
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/* Can't use the common MSI interrupt functions
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* since DMAR is not a pci device
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*/
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@@ -31,6 +31,7 @@
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#include <linux/list.h>
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#include <linux/iommu.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/dmar.h>
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#include <asm/cacheflush.h>
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#include <asm/iommu.h>
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@@ -114,6 +115,7 @@
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* Extended Capability Register
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*/
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#define ecap_dit(e) ((e >> 41) & 0x1)
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#define ecap_pasid(e) ((e >> 40) & 0x1)
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#define ecap_pss(e) ((e >> 35) & 0x1f)
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#define ecap_eafs(e) ((e >> 34) & 0x1)
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@@ -284,6 +286,7 @@ enum {
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#define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
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#define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
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#define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
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#define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
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#define QI_DEV_IOTLB_SIZE 1
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#define QI_DEV_IOTLB_MAX_INVS 32
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@@ -308,6 +311,7 @@ enum {
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#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
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#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
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#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
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#define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
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#define QI_DEV_EIOTLB_MAX_INVS 32
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#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
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@@ -385,6 +389,42 @@ struct pasid_entry;
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struct pasid_state_entry;
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struct page_req_dsc;
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struct dmar_domain {
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int nid; /* node id */
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unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED];
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/* Refcount of devices per iommu */
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u16 iommu_did[DMAR_UNITS_SUPPORTED];
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/* Domain ids per IOMMU. Use u16 since
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* domain ids are 16 bit wide according
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* to VT-d spec, section 9.3 */
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bool has_iotlb_device;
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struct list_head devices; /* all devices' list */
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struct iova_domain iovad; /* iova's that belong to this domain */
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struct dma_pte *pgd; /* virtual address */
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int gaw; /* max guest address width */
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/* adjusted guest address width, 0 is level 2 30-bit */
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int agaw;
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int flags; /* flags to find out type of domain */
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int iommu_coherency;/* indicate coherency of iommu access */
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int iommu_snooping; /* indicate snooping control feature*/
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int iommu_count; /* reference count of iommu */
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int iommu_superpage;/* Level of superpages supported:
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0 == 4KiB (no superpages), 1 == 2MiB,
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2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
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u64 max_addr; /* maximum mapped address */
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struct iommu_domain domain; /* generic domain data structure for
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iommu core */
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};
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struct intel_iommu {
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void __iomem *reg; /* Pointer to hardware regs, virtual addr */
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u64 reg_phys; /* physical address of hw register set */
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@@ -414,11 +454,9 @@ struct intel_iommu {
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* devices away to userspace processes (e.g. for DPDK) and don't
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* want to trust that userspace will use *only* the PASID it was
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* told to. But while it's all driver-arbitrated, we're fine. */
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struct pasid_entry *pasid_table;
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struct pasid_state_entry *pasid_state_table;
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struct page_req_dsc *prq;
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unsigned char prq_name[16]; /* Name for PRQ interrupt */
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struct idr pasid_idr;
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u32 pasid_max;
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#endif
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struct q_inval *qi; /* Queued invalidation info */
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@@ -434,6 +472,27 @@ struct intel_iommu {
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u32 flags; /* Software defined flags */
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};
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/* PCI domain-device relationship */
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struct device_domain_info {
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struct list_head link; /* link to domain siblings */
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struct list_head global; /* link to global list */
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struct list_head table; /* link to pasid table */
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u8 bus; /* PCI bus number */
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u8 devfn; /* PCI devfn number */
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u16 pfsid; /* SRIOV physical function source ID */
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u8 pasid_supported:3;
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u8 pasid_enabled:1;
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u8 pri_supported:1;
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u8 pri_enabled:1;
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u8 ats_supported:1;
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u8 ats_enabled:1;
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u8 ats_qdep;
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struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
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struct intel_iommu *iommu; /* IOMMU used by this device */
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struct dmar_domain *domain; /* pointer to domain */
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struct pasid_table *pasid_table; /* pasid table */
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};
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static inline void __iommu_flush_cache(
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struct intel_iommu *iommu, void *addr, int size)
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{
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@@ -453,16 +512,22 @@ extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
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u8 fm, u64 type);
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extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
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unsigned int size_order, u64 type);
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extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
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u64 addr, unsigned mask);
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extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
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u16 qdep, u64 addr, unsigned mask);
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extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
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extern int dmar_ir_support(void);
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struct dmar_domain *get_valid_domain_for_dev(struct device *dev);
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void *alloc_pgtable_page(int node);
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void free_pgtable_page(void *vaddr);
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struct intel_iommu *domain_get_iommu(struct dmar_domain *domain);
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int for_each_device_domain(int (*fn)(struct device_domain_info *info,
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void *data), void *data);
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#ifdef CONFIG_INTEL_IOMMU_SVM
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extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu);
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extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu);
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int intel_svm_init(struct intel_iommu *iommu);
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int intel_svm_exit(struct intel_iommu *iommu);
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extern int intel_svm_enable_prq(struct intel_iommu *iommu);
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extern int intel_svm_finish_prq(struct intel_iommu *iommu);
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@@ -486,6 +551,7 @@ struct intel_svm {
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int flags;
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int pasid;
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struct list_head devs;
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struct list_head list;
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};
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extern int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev);
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@@ -166,8 +166,6 @@ struct iommu_resv_region {
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* @detach_dev: detach device from an iommu domain
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* @map: map a physically contiguous memory region to an iommu domain
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* @unmap: unmap a physically contiguous memory region from an iommu domain
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* @map_sg: map a scatter-gather list of physically contiguous memory chunks
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* to an iommu domain
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* @flush_tlb_all: Synchronously flush all hardware TLBs for this domain
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* @tlb_range_add: Add a given iova range to the flush queue for this domain
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* @tlb_sync: Flush all queued ranges from the hardware TLBs and empty flush
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@@ -201,8 +199,6 @@ struct iommu_ops {
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phys_addr_t paddr, size_t size, int prot);
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size_t (*unmap)(struct iommu_domain *domain, unsigned long iova,
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size_t size);
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size_t (*map_sg)(struct iommu_domain *domain, unsigned long iova,
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struct scatterlist *sg, unsigned int nents, int prot);
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void (*flush_iotlb_all)(struct iommu_domain *domain);
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void (*iotlb_range_add)(struct iommu_domain *domain,
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unsigned long iova, size_t size);
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@@ -303,9 +299,8 @@ extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova,
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size_t size);
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extern size_t iommu_unmap_fast(struct iommu_domain *domain,
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unsigned long iova, size_t size);
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extern size_t default_iommu_map_sg(struct iommu_domain *domain, unsigned long iova,
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struct scatterlist *sg,unsigned int nents,
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int prot);
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extern size_t iommu_map_sg(struct iommu_domain *domain, unsigned long iova,
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struct scatterlist *sg,unsigned int nents, int prot);
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extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova);
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extern void iommu_set_fault_handler(struct iommu_domain *domain,
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iommu_fault_handler_t handler, void *token);
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@@ -378,13 +373,6 @@ static inline void iommu_tlb_sync(struct iommu_domain *domain)
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domain->ops->iotlb_sync(domain);
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}
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static inline size_t iommu_map_sg(struct iommu_domain *domain,
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unsigned long iova, struct scatterlist *sg,
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unsigned int nents, int prot)
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{
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return domain->ops->map_sg(domain, iova, sg, nents, prot);
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}
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/* PCI device grouping function */
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extern struct iommu_group *pci_device_group(struct device *dev);
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/* Generic device grouping function */
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@@ -698,4 +686,11 @@ const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode)
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#endif /* CONFIG_IOMMU_API */
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#ifdef CONFIG_IOMMU_DEBUGFS
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extern struct dentry *iommu_debugfs_dir;
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void iommu_debugfs_setup(void);
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#else
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static inline void iommu_debugfs_setup(void) {}
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#endif
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#endif /* __LINUX_IOMMU_H */
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@@ -1,18 +0,0 @@
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/* sh_ipmmu.h
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*
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* Copyright (C) 2012 Hideki EIRAKU
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __SH_IPMMU_H__
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#define __SH_IPMMU_H__
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struct shmobile_ipmmu_platform_data {
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const char * const *dev_names;
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unsigned int num_dev_names;
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};
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#endif /* __SH_IPMMU_H__ */
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