clk: sprd: add gate for pll clocks
Some sprd's gate clocks are used to the switch of pll, which need to wait a certain time for stable after being enabled. Signed-off-by: Xiaolong Zhang <xiaolong.zhang@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-2-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Stephen Boyd

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bb6d3fb354
commit
187e5cd2d1
@@ -79,6 +79,17 @@ static int sprd_sc_gate_enable(struct clk_hw *hw)
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return 0;
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}
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static int sprd_pll_sc_gate_prepare(struct clk_hw *hw)
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{
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struct sprd_gate *sg = hw_to_sprd_gate(hw);
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clk_sc_gate_toggle(sg, true);
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udelay(sg->udelay);
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return 0;
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}
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static int sprd_gate_is_enabled(struct clk_hw *hw)
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{
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struct sprd_gate *sg = hw_to_sprd_gate(hw);
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@@ -109,3 +120,9 @@ const struct clk_ops sprd_sc_gate_ops = {
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};
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EXPORT_SYMBOL_GPL(sprd_sc_gate_ops);
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const struct clk_ops sprd_pll_sc_gate_ops = {
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.unprepare = sprd_sc_gate_disable,
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.prepare = sprd_pll_sc_gate_prepare,
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.is_enabled = sprd_gate_is_enabled,
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};
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EXPORT_SYMBOL_GPL(sprd_pll_sc_gate_ops);
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