irqchip: mips-gic: Stop using per-platform mapping tables
Now that the GIC properly uses IRQ domains, kill off the per-platform routing tables that were used to make the GIC appear transparent. This includes: - removing the mapping tables and the support for applying them, - moving GIC IPI support to the GIC driver, - properly routing the i8259 through the GIC on Malta, and - updating IRQ assignments on SEAD-3 when the GIC is present. Platforms no longer will pass an interrupt mapping table to gic_init. Instead, they will pass the CPU interrupt vector (2 - 7) that they expect the GIC to route interrupts to. Note that in EIC mode this value is ignored and all GIC interrupts are routed to EIC vector 1. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7816/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Andrew Bresticker
committed by
Ralf Baechle
Ralf Baechle
szülő
c49581a4df
commit
18743d2781
@@ -8,6 +8,8 @@
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*/
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#include <linux/bitmap.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <linux/clocksource.h>
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@@ -22,11 +24,8 @@
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unsigned int gic_frequency;
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unsigned int gic_present;
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unsigned long _gic_base;
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unsigned int gic_irq_base;
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unsigned int gic_irq_flags[GIC_NUM_INTRS];
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/* The index into this array is the vector # of the interrupt. */
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struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
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unsigned int gic_cpu_pin;
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struct gic_pcpu_mask {
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DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
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@@ -46,6 +45,8 @@ static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
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static DEFINE_SPINLOCK(gic_lock);
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static struct irq_domain *gic_irq_domain;
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static void __gic_irq_dispatch(void);
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#if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC)
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cycle_t gic_read_count(void)
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{
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@@ -117,21 +118,6 @@ void gic_send_ipi(unsigned int intr)
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GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
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}
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static void gic_eic_irq_dispatch(void)
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{
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unsigned int cause = read_c0_cause();
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int irq;
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irq = (cause & ST0_IM) >> STATUSB_IP2;
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if (irq == 0)
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irq = -1;
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if (irq >= 0)
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do_IRQ(gic_irq_base + irq);
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else
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spurious_interrupt();
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}
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static void __init vpe_local_setup(unsigned int numvpes)
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{
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unsigned long timer_intr = GIC_INT_TMR;
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@@ -166,16 +152,15 @@ static void __init vpe_local_setup(unsigned int numvpes)
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GIC_MAP_TO_PIN_MSK | timer_intr);
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if (cpu_has_veic) {
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set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
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gic_eic_irq_dispatch);
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gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
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__gic_irq_dispatch);
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}
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if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
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GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
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GIC_MAP_TO_PIN_MSK | perf_intr);
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if (cpu_has_veic) {
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set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
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gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
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set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET,
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__gic_irq_dispatch);
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}
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}
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}
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@@ -343,64 +328,100 @@ static struct irq_chip gic_irq_controller = {
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#endif
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};
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static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
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unsigned int pin, unsigned int polarity, unsigned int trigtype,
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unsigned int flags)
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static void __gic_irq_dispatch(void)
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{
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struct gic_shared_intr_map *map_ptr;
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unsigned int intr, virq;
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while ((intr = gic_get_int()) != GIC_NUM_INTRS) {
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virq = irq_linear_revmap(gic_irq_domain, intr);
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do_IRQ(virq);
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}
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}
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static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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{
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__gic_irq_dispatch();
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}
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#ifdef CONFIG_MIPS_GIC_IPI
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static int gic_resched_int_base;
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static int gic_call_int_base;
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unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
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{
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return gic_resched_int_base + cpu;
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}
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unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
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{
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return gic_call_int_base + cpu;
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}
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static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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{
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scheduler_ipi();
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return IRQ_HANDLED;
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}
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static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
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{
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smp_call_function_interrupt();
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return IRQ_HANDLED;
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}
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static struct irqaction irq_resched = {
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.handler = ipi_resched_interrupt,
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.flags = IRQF_PERCPU,
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.name = "IPI resched"
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};
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static struct irqaction irq_call = {
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.handler = ipi_call_interrupt,
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.flags = IRQF_PERCPU,
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.name = "IPI call"
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};
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static __init void gic_ipi_init_one(unsigned int intr, int cpu,
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struct irqaction *action)
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{
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int virq = irq_create_mapping(gic_irq_domain, intr);
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int i;
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/* Setup Intr to Pin mapping */
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if (pin & GIC_MAP_TO_NMI_MSK) {
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int i;
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
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/* FIXME: hack to route NMI to all cpu's */
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for (i = 0; i < NR_CPUS; i += 32) {
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GICWRITE(GIC_REG_ADDR(SHARED,
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GIC_SH_MAP_TO_VPE_REG_OFF(intr, i)),
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0xffffffff);
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}
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} else {
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
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GIC_MAP_TO_PIN_MSK | pin);
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/* Setup Intr to CPU mapping */
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GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
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if (cpu_has_veic) {
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set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
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gic_eic_irq_dispatch);
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map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
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if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
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BUG();
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map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
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}
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}
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/* Setup Intr Polarity */
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GIC_SET_POLARITY(intr, polarity);
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/* Setup Intr Trigger Type */
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GIC_SET_TRIGGER(intr, trigtype);
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/* Init Intr Masks */
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GIC_CLR_INTR_MASK(intr);
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/* Initialise per-cpu Interrupt software masks */
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GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
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for (i = 0; i < NR_CPUS; i++)
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clear_bit(intr, pcpu_masks[i].pcpu_mask);
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set_bit(intr, pcpu_masks[cpu].pcpu_mask);
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if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
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GIC_SET_INTR_MASK(intr);
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if (trigtype == GIC_TRIG_EDGE)
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gic_irq_flags[intr] |= GIC_TRIG_EDGE;
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irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
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irq_set_handler(virq, handle_percpu_irq);
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setup_irq(virq, action);
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}
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static void __init gic_basic_init(int numintrs, int numvpes,
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struct gic_intr_map *intrmap, int mapsize)
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static __init void gic_ipi_init(void)
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{
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unsigned int i, cpu;
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unsigned int pin_offset = 0;
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int i;
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/* Use last 2 * NR_CPUS interrupts as IPIs */
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gic_resched_int_base = GIC_NUM_INTRS - nr_cpu_ids;
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gic_call_int_base = gic_resched_int_base - nr_cpu_ids;
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for (i = 0; i < nr_cpu_ids; i++) {
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gic_ipi_init_one(gic_call_int_base + i, i, &irq_call);
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gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched);
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}
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}
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#else
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static inline void gic_ipi_init(void)
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{
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}
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#endif
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static void __init gic_basic_init(int numintrs, int numvpes)
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{
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unsigned int i;
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board_bind_eic_interrupt = &gic_bind_eic_interrupt;
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@@ -409,31 +430,8 @@ static void __init gic_basic_init(int numintrs, int numvpes,
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GIC_SET_POLARITY(i, GIC_POL_POS);
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GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
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GIC_CLR_INTR_MASK(i);
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if (i < GIC_NUM_INTRS) {
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if (i < GIC_NUM_INTRS)
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gic_irq_flags[i] = 0;
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gic_shared_intr_map[i].num_shared_intr = 0;
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gic_shared_intr_map[i].local_intr_mask = 0;
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}
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}
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/*
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* In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
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* one because the GIC will add one (since 0=no intr).
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*/
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if (cpu_has_veic)
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pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
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/* Setup specifics */
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for (i = 0; i < mapsize; i++) {
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cpu = intrmap[i].cpunum;
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if (cpu == GIC_UNUSED)
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continue;
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gic_setup_intr(i,
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intrmap[i].cpunum,
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intrmap[i].pin + pin_offset,
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intrmap[i].polarity,
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intrmap[i].trigtype,
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intrmap[i].flags);
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}
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vpe_local_setup(numvpes);
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@@ -448,7 +446,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
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spin_lock_irqsave(&gic_lock, flags);
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GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(hw)),
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GIC_MAP_TO_PIN_MSK | 0);
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GIC_MAP_TO_PIN_MSK | gic_cpu_pin);
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/* Map to VPE 0 by default */
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GIC_SH_MAP_TO_VPE_SMASK(hw, 0);
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set_bit(hw, pcpu_masks[0].pcpu_mask);
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@@ -463,8 +461,7 @@ static struct irq_domain_ops gic_irq_domain_ops = {
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};
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void __init gic_init(unsigned long gic_base_addr,
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unsigned long gic_addrspace_size,
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struct gic_intr_map *intr_map, unsigned int intr_map_size,
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unsigned long gic_addrspace_size, unsigned int cpu_vec,
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unsigned int irqbase)
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{
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unsigned int gicconfig;
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@@ -472,7 +469,6 @@ void __init gic_init(unsigned long gic_base_addr,
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_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
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gic_addrspace_size);
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gic_irq_base = irqbase;
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GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
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numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
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@@ -483,10 +479,23 @@ void __init gic_init(unsigned long gic_base_addr,
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GIC_SH_CONFIG_NUMVPES_SHF;
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numvpes = numvpes + 1;
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if (cpu_has_veic) {
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/* Always use vector 1 in EIC mode */
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gic_cpu_pin = 0;
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set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
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__gic_irq_dispatch);
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} else {
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gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
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irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
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gic_irq_dispatch);
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}
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gic_irq_domain = irq_domain_add_simple(NULL, GIC_NUM_INTRS, irqbase,
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&gic_irq_domain_ops, NULL);
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if (!gic_irq_domain)
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panic("Failed to add GIC IRQ domain");
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gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
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gic_basic_init(numintrs, numvpes);
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gic_ipi_init();
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}
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