Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (99 commits) drivers/virt: add missing linux/interrupt.h to fsl_hypervisor.c powerpc/85xx: fix mpic configuration in CAMP mode powerpc: Copy back TIF flags on return from softirq stack powerpc/64: Make server perfmon only built on ppc64 server devices powerpc/pseries: Fix hvc_vio.c build due to recent changes powerpc: Exporting boot_cpuid_phys powerpc: Add CFAR to oops output hvc_console: Add kdb support powerpc/pseries: Fix hvterm_raw_get_chars to accept < 16 chars, fixing xmon powerpc/irq: Quieten irq mapping printks powerpc: Enable lockup and hung task detectors in pseries and ppc64 defeconfigs powerpc: Add mpt2sas driver to pseries and ppc64 defconfig powerpc: Disable IRQs off tracer in ppc64 defconfig powerpc: Sync pseries and ppc64 defconfigs powerpc/pseries/hvconsole: Fix dropped console output hvc_console: Improve tty/console put_chars handling powerpc/kdump: Fix timeout in crash_kexec_wait_realmode powerpc/mm: Fix output of total_ram. powerpc/cpufreq: Add cpufreq driver for Momentum Maple boards powerpc: Correct annotations of pmu registration functions ... Fix up trivial Kconfig/Makefile conflicts in arch/powerpc, drivers, and drivers/cpufreq
Este commit está contenido en:
Linus Torvalds
@@ -4,6 +4,7 @@ ccflags-$(CONFIG_PPC64) := -mno-minimal-toc
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mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
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obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
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obj-$(CONFIG_PPC_EPAPR_HV_PIC) += ehv_pic.o
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fsl-msi-obj-$(CONFIG_PCI_MSI) += fsl_msi.o
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obj-$(CONFIG_PPC_MSI_BITMAP) += msi_bitmap.o
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302
arch/powerpc/sysdev/ehv_pic.c
Archivo normal
302
arch/powerpc/sysdev/ehv_pic.c
Archivo normal
@@ -0,0 +1,302 @@
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/*
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* Driver for ePAPR Embedded Hypervisor PIC
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*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* Author: Ashish Kalra <ashish.kalra@freescale.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/smp.h>
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#include <asm/machdep.h>
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#include <asm/ehv_pic.h>
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#include <asm/fsl_hcalls.h>
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#include "../../../kernel/irq/settings.h"
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static struct ehv_pic *global_ehv_pic;
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static DEFINE_SPINLOCK(ehv_pic_lock);
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static u32 hwirq_intspec[NR_EHV_PIC_INTS];
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static u32 __iomem *mpic_percpu_base_vaddr;
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#define IRQ_TYPE_MPIC_DIRECT 4
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#define MPIC_EOI 0x00B0
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/*
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* Linux descriptor level callbacks
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*/
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void ehv_pic_unmask_irq(struct irq_data *d)
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{
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unsigned int src = virq_to_hw(d->irq);
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ev_int_set_mask(src, 0);
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}
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void ehv_pic_mask_irq(struct irq_data *d)
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{
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unsigned int src = virq_to_hw(d->irq);
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ev_int_set_mask(src, 1);
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}
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void ehv_pic_end_irq(struct irq_data *d)
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{
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unsigned int src = virq_to_hw(d->irq);
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ev_int_eoi(src);
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}
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void ehv_pic_direct_end_irq(struct irq_data *d)
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{
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out_be32(mpic_percpu_base_vaddr + MPIC_EOI / 4, 0);
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}
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int ehv_pic_set_affinity(struct irq_data *d, const struct cpumask *dest,
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bool force)
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{
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unsigned int src = virq_to_hw(d->irq);
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unsigned int config, prio, cpu_dest;
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int cpuid = irq_choose_cpu(dest);
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unsigned long flags;
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spin_lock_irqsave(&ehv_pic_lock, flags);
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ev_int_get_config(src, &config, &prio, &cpu_dest);
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ev_int_set_config(src, config, prio, cpuid);
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spin_unlock_irqrestore(&ehv_pic_lock, flags);
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return 0;
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}
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static unsigned int ehv_pic_type_to_vecpri(unsigned int type)
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{
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/* Now convert sense value */
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
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EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_EDGE_BOTH:
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return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
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EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
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case IRQ_TYPE_LEVEL_HIGH:
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return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
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EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
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case IRQ_TYPE_LEVEL_LOW:
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default:
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return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
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EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
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}
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}
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int ehv_pic_set_irq_type(struct irq_data *d, unsigned int flow_type)
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{
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unsigned int src = virq_to_hw(d->irq);
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struct irq_desc *desc = irq_to_desc(d->irq);
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unsigned int vecpri, vold, vnew, prio, cpu_dest;
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unsigned long flags;
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if (flow_type == IRQ_TYPE_NONE)
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flow_type = IRQ_TYPE_LEVEL_LOW;
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irq_settings_clr_level(desc);
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irq_settings_set_trigger_mask(desc, flow_type);
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if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
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irq_settings_set_level(desc);
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vecpri = ehv_pic_type_to_vecpri(flow_type);
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spin_lock_irqsave(&ehv_pic_lock, flags);
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ev_int_get_config(src, &vold, &prio, &cpu_dest);
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vnew = vold & ~(EHV_PIC_INFO(VECPRI_POLARITY_MASK) |
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EHV_PIC_INFO(VECPRI_SENSE_MASK));
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vnew |= vecpri;
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/*
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* TODO : Add specific interface call for platform to set
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* individual interrupt priorities.
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* platform currently using static/default priority for all ints
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*/
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prio = 8;
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ev_int_set_config(src, vecpri, prio, cpu_dest);
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spin_unlock_irqrestore(&ehv_pic_lock, flags);
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return 0;
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}
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static struct irq_chip ehv_pic_irq_chip = {
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.irq_mask = ehv_pic_mask_irq,
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.irq_unmask = ehv_pic_unmask_irq,
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.irq_eoi = ehv_pic_end_irq,
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.irq_set_type = ehv_pic_set_irq_type,
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};
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static struct irq_chip ehv_pic_direct_eoi_irq_chip = {
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.irq_mask = ehv_pic_mask_irq,
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.irq_unmask = ehv_pic_unmask_irq,
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.irq_eoi = ehv_pic_direct_end_irq,
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.irq_set_type = ehv_pic_set_irq_type,
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};
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/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
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unsigned int ehv_pic_get_irq(void)
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{
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int irq;
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BUG_ON(global_ehv_pic == NULL);
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if (global_ehv_pic->coreint_flag)
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irq = mfspr(SPRN_EPR); /* if core int mode */
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else
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ev_int_iack(0, &irq); /* legacy mode */
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if (irq == 0xFFFF) /* 0xFFFF --> no irq is pending */
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return NO_IRQ;
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/*
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* this will also setup revmap[] in the slow path for the first
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* time, next calls will always use fast path by indexing revmap
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*/
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return irq_linear_revmap(global_ehv_pic->irqhost, irq);
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}
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static int ehv_pic_host_match(struct irq_host *h, struct device_node *node)
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{
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/* Exact match, unless ehv_pic node is NULL */
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return h->of_node == NULL || h->of_node == node;
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}
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static int ehv_pic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct ehv_pic *ehv_pic = h->host_data;
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struct irq_chip *chip;
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/* Default chip */
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chip = &ehv_pic->hc_irq;
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if (mpic_percpu_base_vaddr)
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if (hwirq_intspec[hw] & IRQ_TYPE_MPIC_DIRECT)
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chip = &ehv_pic_direct_eoi_irq_chip;
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irq_set_chip_data(virq, chip);
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/*
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* using handle_fasteoi_irq as our irq handler, this will
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* only call the eoi callback and suitable for the MPIC
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* controller which set ISR/IPR automatically and clear the
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* highest priority active interrupt in ISR/IPR when we do
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* a specific eoi
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*/
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irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
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/* Set default irq type */
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irq_set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static int ehv_pic_host_xlate(struct irq_host *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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/*
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* interrupt sense values coming from the guest device tree
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* interrupt specifiers can have four possible sense and
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* level encoding information and they need to
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* be translated between firmware type & linux type.
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*/
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static unsigned char map_of_senses_to_linux_irqtype[4] = {
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IRQ_TYPE_EDGE_FALLING,
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IRQ_TYPE_EDGE_RISING,
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IRQ_TYPE_LEVEL_LOW,
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IRQ_TYPE_LEVEL_HIGH,
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};
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*out_hwirq = intspec[0];
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if (intsize > 1) {
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hwirq_intspec[intspec[0]] = intspec[1];
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*out_flags = map_of_senses_to_linux_irqtype[intspec[1] &
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~IRQ_TYPE_MPIC_DIRECT];
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} else {
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*out_flags = IRQ_TYPE_NONE;
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}
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return 0;
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}
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static struct irq_host_ops ehv_pic_host_ops = {
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.match = ehv_pic_host_match,
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.map = ehv_pic_host_map,
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.xlate = ehv_pic_host_xlate,
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};
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void __init ehv_pic_init(void)
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{
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struct device_node *np, *np2;
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struct ehv_pic *ehv_pic;
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int coreint_flag = 1;
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np = of_find_compatible_node(NULL, NULL, "epapr,hv-pic");
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if (!np) {
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pr_err("ehv_pic_init: could not find epapr,hv-pic node\n");
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return;
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}
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if (!of_find_property(np, "has-external-proxy", NULL))
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coreint_flag = 0;
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ehv_pic = kzalloc(sizeof(struct ehv_pic), GFP_KERNEL);
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if (!ehv_pic) {
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of_node_put(np);
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return;
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}
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ehv_pic->irqhost = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
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NR_EHV_PIC_INTS, &ehv_pic_host_ops, 0);
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if (!ehv_pic->irqhost) {
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of_node_put(np);
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return;
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}
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np2 = of_find_compatible_node(NULL, NULL, "fsl,hv-mpic-per-cpu");
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if (np2) {
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mpic_percpu_base_vaddr = of_iomap(np2, 0);
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if (!mpic_percpu_base_vaddr)
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pr_err("ehv_pic_init: of_iomap failed\n");
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of_node_put(np2);
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}
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ehv_pic->irqhost->host_data = ehv_pic;
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ehv_pic->hc_irq = ehv_pic_irq_chip;
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ehv_pic->hc_irq.irq_set_affinity = ehv_pic_set_affinity;
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ehv_pic->coreint_flag = coreint_flag;
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global_ehv_pic = ehv_pic;
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irq_set_default_host(global_ehv_pic->irqhost);
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}
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@@ -38,10 +38,17 @@ static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
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static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
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{
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u8 progif;
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/* if we aren't a PCIe don't bother */
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if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
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return;
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/* if we aren't in host mode don't bother */
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pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
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if (progif & 0x1)
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return;
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dev->class = PCI_CLASS_BRIDGE_PCI << 8;
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fsl_pcie_bus_fixup = 1;
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return;
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@@ -323,6 +330,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
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struct pci_controller *hose;
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struct resource rsrc;
|
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const int *bus_range;
|
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u8 progif;
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if (!of_device_is_available(dev)) {
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pr_warning("%s: disabled\n", dev->full_name);
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@@ -353,6 +361,18 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
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PPC_INDIRECT_TYPE_BIG_ENDIAN);
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early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
|
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if ((progif & 1) == 1) {
|
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/* unmap cfg_data & cfg_addr separately if not on same page */
|
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if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
|
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((unsigned long)hose->cfg_addr & PAGE_MASK))
|
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iounmap(hose->cfg_data);
|
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iounmap(hose->cfg_addr);
|
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pcibios_free_controller(hose);
|
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return 0;
|
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}
|
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|
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setup_pci_cmd(hose);
|
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|
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/* check PCI express link status */
|
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@@ -380,70 +400,11 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
|
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|
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return 0;
|
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}
|
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|
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
|
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
|
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
|
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
|
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
|
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
|
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
|
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header);
|
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020, quirk_fsl_pcie_header);
|
||||
#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
|
||||
|
||||
#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
|
||||
|
||||
#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
|
||||
struct mpc83xx_pcie_priv {
|
||||
void __iomem *cfg_type0;
|
||||
void __iomem *cfg_type1;
|
||||
|
||||
@@ -41,6 +41,7 @@
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/cpm2.h>
|
||||
#include <asm/fsl_hcalls.h> /* For the Freescale hypervisor */
|
||||
|
||||
extern void init_fcc_ioports(struct fs_platform_info*);
|
||||
extern void init_fec_ioports(struct fs_platform_info*);
|
||||
@@ -252,3 +253,29 @@ void fsl_rstcr_restart(char *cmd)
|
||||
struct platform_diu_data_ops diu_ops;
|
||||
EXPORT_SYMBOL(diu_ops);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Restart the current partition
|
||||
*
|
||||
* This function should be assigned to the ppc_md.restart function pointer,
|
||||
* to initiate a partition restart when we're running under the Freescale
|
||||
* hypervisor.
|
||||
*/
|
||||
void fsl_hv_restart(char *cmd)
|
||||
{
|
||||
pr_info("hv restart\n");
|
||||
fh_partition_restart(-1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Halt the current partition
|
||||
*
|
||||
* This function should be assigned to the ppc_md.power_off and ppc_md.halt
|
||||
* function pointers, to shut down the partition when we're running under
|
||||
* the Freescale hypervisor.
|
||||
*/
|
||||
void fsl_hv_halt(void)
|
||||
{
|
||||
pr_info("hv exit\n");
|
||||
fh_partition_stop(-1);
|
||||
}
|
||||
|
||||
@@ -36,5 +36,8 @@ struct platform_diu_data_ops {
|
||||
extern struct platform_diu_data_ops diu_ops;
|
||||
#endif
|
||||
|
||||
void fsl_hv_restart(char *cmd);
|
||||
void fsl_hv_halt(void);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@@ -598,42 +598,6 @@ static void __init mpic_scan_ht_pics(struct mpic *mpic)
|
||||
|
||||
#endif /* CONFIG_MPIC_U3_HT_IRQS */
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int irq_choose_cpu(const struct cpumask *mask)
|
||||
{
|
||||
int cpuid;
|
||||
|
||||
if (cpumask_equal(mask, cpu_all_mask)) {
|
||||
static int irq_rover = 0;
|
||||
static DEFINE_RAW_SPINLOCK(irq_rover_lock);
|
||||
unsigned long flags;
|
||||
|
||||
/* Round-robin distribution... */
|
||||
do_round_robin:
|
||||
raw_spin_lock_irqsave(&irq_rover_lock, flags);
|
||||
|
||||
irq_rover = cpumask_next(irq_rover, cpu_online_mask);
|
||||
if (irq_rover >= nr_cpu_ids)
|
||||
irq_rover = cpumask_first(cpu_online_mask);
|
||||
|
||||
cpuid = irq_rover;
|
||||
|
||||
raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
|
||||
} else {
|
||||
cpuid = cpumask_first_and(mask, cpu_online_mask);
|
||||
if (cpuid >= nr_cpu_ids)
|
||||
goto do_round_robin;
|
||||
}
|
||||
|
||||
return get_hard_smp_processor_id(cpuid);
|
||||
}
|
||||
#else
|
||||
static int irq_choose_cpu(const struct cpumask *mask)
|
||||
{
|
||||
return hard_smp_processor_id();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Find an mpic associated with a given linux interrupt */
|
||||
static struct mpic *mpic_find(unsigned int irq)
|
||||
{
|
||||
@@ -849,7 +813,7 @@ static void mpic_unmask_tm(struct irq_data *d)
|
||||
struct mpic *mpic = mpic_from_irq_data(d);
|
||||
unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
|
||||
|
||||
DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, irq, src);
|
||||
DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
|
||||
mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
|
||||
mpic_tm_read(src);
|
||||
}
|
||||
|
||||
@@ -650,12 +650,74 @@ struct ppc4xx_pciex_hwops
|
||||
int (*core_init)(struct device_node *np);
|
||||
int (*port_init_hw)(struct ppc4xx_pciex_port *port);
|
||||
int (*setup_utl)(struct ppc4xx_pciex_port *port);
|
||||
void (*check_link)(struct ppc4xx_pciex_port *port);
|
||||
};
|
||||
|
||||
static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
|
||||
|
||||
#ifdef CONFIG_44x
|
||||
|
||||
static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
|
||||
unsigned int sdr_offset,
|
||||
unsigned int mask,
|
||||
unsigned int value,
|
||||
int timeout_ms)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
while(timeout_ms--) {
|
||||
val = mfdcri(SDR0, port->sdr_base + sdr_offset);
|
||||
if ((val & mask) == value) {
|
||||
pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
|
||||
port->index, sdr_offset, timeout_ms, val);
|
||||
return 0;
|
||||
}
|
||||
msleep(1);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
|
||||
{
|
||||
/* Wait for reset to complete */
|
||||
if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
|
||||
printk(KERN_WARNING "PCIE%d: PGRST failed\n",
|
||||
port->index);
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
|
||||
{
|
||||
printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
|
||||
|
||||
/* Check for card presence detect if supported, if not, just wait for
|
||||
* link unconditionally.
|
||||
*
|
||||
* note that we don't fail if there is no link, we just filter out
|
||||
* config space accesses. That way, it will be easier to implement
|
||||
* hotplug later on.
|
||||
*/
|
||||
if (!port->has_ibpre ||
|
||||
!ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
|
||||
1 << 28, 1 << 28, 100)) {
|
||||
printk(KERN_INFO
|
||||
"PCIE%d: Device detected, waiting for link...\n",
|
||||
port->index);
|
||||
if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
|
||||
0x1000, 0x1000, 2000))
|
||||
printk(KERN_WARNING
|
||||
"PCIE%d: Link up failed\n", port->index);
|
||||
else {
|
||||
printk(KERN_INFO
|
||||
"PCIE%d: link is up !\n", port->index);
|
||||
port->link = 1;
|
||||
}
|
||||
} else
|
||||
printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
|
||||
}
|
||||
|
||||
/* Check various reset bits of the 440SPe PCIe core */
|
||||
static int __init ppc440spe_pciex_check_reset(struct device_node *np)
|
||||
{
|
||||
@@ -806,7 +868,7 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
|
||||
dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
|
||||
(1 << 24) | (1 << 16), 1 << 12);
|
||||
|
||||
return 0;
|
||||
return ppc4xx_pciex_port_reset_sdr(port);
|
||||
}
|
||||
|
||||
static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
|
||||
@@ -856,6 +918,7 @@ static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
|
||||
.core_init = ppc440spe_pciex_core_init,
|
||||
.port_init_hw = ppc440speA_pciex_init_port_hw,
|
||||
.setup_utl = ppc440speA_pciex_init_utl,
|
||||
.check_link = ppc4xx_pciex_check_link_sdr,
|
||||
};
|
||||
|
||||
static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
|
||||
@@ -863,6 +926,7 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
|
||||
.core_init = ppc440spe_pciex_core_init,
|
||||
.port_init_hw = ppc440speB_pciex_init_port_hw,
|
||||
.setup_utl = ppc440speB_pciex_init_utl,
|
||||
.check_link = ppc4xx_pciex_check_link_sdr,
|
||||
};
|
||||
|
||||
static int __init ppc460ex_pciex_core_init(struct device_node *np)
|
||||
@@ -944,7 +1008,7 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
|
||||
|
||||
port->has_ibpre = 1;
|
||||
|
||||
return 0;
|
||||
return ppc4xx_pciex_port_reset_sdr(port);
|
||||
}
|
||||
|
||||
static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
|
||||
@@ -972,6 +1036,7 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
|
||||
.core_init = ppc460ex_pciex_core_init,
|
||||
.port_init_hw = ppc460ex_pciex_init_port_hw,
|
||||
.setup_utl = ppc460ex_pciex_init_utl,
|
||||
.check_link = ppc4xx_pciex_check_link_sdr,
|
||||
};
|
||||
|
||||
static int __init ppc460sx_pciex_core_init(struct device_node *np)
|
||||
@@ -1075,7 +1140,7 @@ static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
|
||||
|
||||
port->has_ibpre = 1;
|
||||
|
||||
return 0;
|
||||
return ppc4xx_pciex_port_reset_sdr(port);
|
||||
}
|
||||
|
||||
static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
|
||||
@@ -1089,6 +1154,7 @@ static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
|
||||
.core_init = ppc460sx_pciex_core_init,
|
||||
.port_init_hw = ppc460sx_pciex_init_port_hw,
|
||||
.setup_utl = ppc460sx_pciex_init_utl,
|
||||
.check_link = ppc4xx_pciex_check_link_sdr,
|
||||
};
|
||||
|
||||
#endif /* CONFIG_44x */
|
||||
@@ -1154,7 +1220,7 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
|
||||
|
||||
port->has_ibpre = 1;
|
||||
|
||||
return 0;
|
||||
return ppc4xx_pciex_port_reset_sdr(port);
|
||||
}
|
||||
|
||||
static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
|
||||
@@ -1183,11 +1249,11 @@ static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
|
||||
.core_init = ppc405ex_pciex_core_init,
|
||||
.port_init_hw = ppc405ex_pciex_init_port_hw,
|
||||
.setup_utl = ppc405ex_pciex_init_utl,
|
||||
.check_link = ppc4xx_pciex_check_link_sdr,
|
||||
};
|
||||
|
||||
#endif /* CONFIG_40x */
|
||||
|
||||
|
||||
/* Check that the core has been initied and if not, do it */
|
||||
static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
|
||||
{
|
||||
@@ -1261,26 +1327,6 @@ static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port
|
||||
dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
|
||||
}
|
||||
|
||||
static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
|
||||
unsigned int sdr_offset,
|
||||
unsigned int mask,
|
||||
unsigned int value,
|
||||
int timeout_ms)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
while(timeout_ms--) {
|
||||
val = mfdcri(SDR0, port->sdr_base + sdr_offset);
|
||||
if ((val & mask) == value) {
|
||||
pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
|
||||
port->index, sdr_offset, timeout_ms, val);
|
||||
return 0;
|
||||
}
|
||||
msleep(1);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
|
||||
{
|
||||
int rc = 0;
|
||||
@@ -1291,40 +1337,8 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
|
||||
if (rc != 0)
|
||||
return rc;
|
||||
|
||||
printk(KERN_INFO "PCIE%d: Checking link...\n",
|
||||
port->index);
|
||||
|
||||
/* Wait for reset to complete */
|
||||
if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
|
||||
printk(KERN_WARNING "PCIE%d: PGRST failed\n",
|
||||
port->index);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check for card presence detect if supported, if not, just wait for
|
||||
* link unconditionally.
|
||||
*
|
||||
* note that we don't fail if there is no link, we just filter out
|
||||
* config space accesses. That way, it will be easier to implement
|
||||
* hotplug later on.
|
||||
*/
|
||||
if (!port->has_ibpre ||
|
||||
!ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
|
||||
1 << 28, 1 << 28, 100)) {
|
||||
printk(KERN_INFO
|
||||
"PCIE%d: Device detected, waiting for link...\n",
|
||||
port->index);
|
||||
if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
|
||||
0x1000, 0x1000, 2000))
|
||||
printk(KERN_WARNING
|
||||
"PCIE%d: Link up failed\n", port->index);
|
||||
else {
|
||||
printk(KERN_INFO
|
||||
"PCIE%d: link is up !\n", port->index);
|
||||
port->link = 1;
|
||||
}
|
||||
} else
|
||||
printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
|
||||
if (ppc4xx_pciex_hwops->check_link)
|
||||
ppc4xx_pciex_hwops->check_link(port);
|
||||
|
||||
/*
|
||||
* Initialize mapping: disable all regions and configure
|
||||
@@ -1347,14 +1361,17 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
|
||||
/*
|
||||
* Check for VC0 active and assert RDY.
|
||||
*/
|
||||
if (port->link &&
|
||||
ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
|
||||
1 << 16, 1 << 16, 5000)) {
|
||||
printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
|
||||
port->link = 0;
|
||||
if (port->sdr_base) {
|
||||
if (port->link &&
|
||||
ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
|
||||
1 << 16, 1 << 16, 5000)) {
|
||||
printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
|
||||
port->link = 0;
|
||||
}
|
||||
|
||||
dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
|
||||
}
|
||||
|
||||
dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
|
||||
msleep(100);
|
||||
|
||||
return 0;
|
||||
|
||||
Referencia en una nueva incidencia
Block a user