ath9k: Fix a PLL hang issue observed with AR9485.
When this PLL hang issue is seen, both Rx and Tx fail to work. The sqsum_dvc needs to be below 2000 for a good chip. During this issue the sqsum_dvc value is beyond 80000 and only a full reset can solve this problem. Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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committed by
John W. Linville

parent
b141581923
commit
181fb18daa
@@ -2091,6 +2091,28 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
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}
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}
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static void ath_hw_pll_work(struct work_struct *work)
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{
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struct ath_softc *sc = container_of(work, struct ath_softc,
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hw_pll_work.work);
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static int count;
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if (AR_SREV_9485(sc->sc_ah)) {
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if (ar9003_get_pll_sqsum_dvc(sc->sc_ah) >= 0x40000) {
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count++;
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if (count == 3) {
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/* Rx is hung for more than 500ms. Reset it */
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ath_reset(sc, true);
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count = 0;
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}
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} else
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count = 0;
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ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
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}
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}
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static void ath_tx_complete_poll_work(struct work_struct *work)
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{
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struct ath_softc *sc = container_of(work, struct ath_softc,
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@@ -2312,6 +2334,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
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}
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INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
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INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
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if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
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error = ath_tx_edma_init(sc);
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