ath9k: Fix a PLL hang issue observed with AR9485.
When this PLL hang issue is seen, both Rx and Tx fail to work. The sqsum_dvc needs to be below 2000 for a good chip. During this issue the sqsum_dvc value is beyond 80000 and only a full reset can solve this problem. Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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committed by
John W. Linville

parent
b141581923
commit
181fb18daa
@@ -230,6 +230,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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cancel_work_sync(&sc->paprd_work);
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cancel_work_sync(&sc->hw_check_work);
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cancel_delayed_work_sync(&sc->tx_complete_work);
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cancel_delayed_work_sync(&sc->hw_pll_work);
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ath9k_ps_wakeup(sc);
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@@ -290,6 +291,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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if (sc->sc_flags & SC_OP_BEACONS)
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ath_beacon_config(sc, NULL);
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ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
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ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
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ath_start_ani(common);
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}
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@@ -1263,6 +1265,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
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cancel_delayed_work_sync(&sc->ath_led_blink_work);
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cancel_delayed_work_sync(&sc->tx_complete_work);
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cancel_delayed_work_sync(&sc->hw_pll_work);
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cancel_work_sync(&sc->paprd_work);
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cancel_work_sync(&sc->hw_check_work);
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