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Merge tag 'for-v4.6-rc/omap-fixes-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.6/fixes

Browse Source 
ARM: OMAP2+: first hwmod fix for v4.6-rc

Fix a longstanding bug in the hwmod code that could cause
hardware SYSCONFIG register values to not match the kernel's
idea of what they should be, and that could result in lower
performance during IP block idle entry.

Basic build, boot, and PM test logs are available here:

http://www.pwsan.com/omap/testlogs/omap-hwmod-fixes-a-for-v4.6-rc/20160326231727/
This commit is contained in:
Tony Lindgren
2016-03-30 10:36:06 -07:00
parent ebf2441480 3ca4a23810
commit 1809de7e7d
10202 changed files with 524032 additions and 307940 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/mach-omap2/Makefile.boot
View File

@@ -1,3 +0,0 @@
zreladdr-y += 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000

22
arch/arm/mach-omap2/board-generic.c
View File

@@ -18,6 +18,7 @@
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/system_info.h>
#include "common.h"
@@ -77,12 +78,31 @@ static const char *const n900_boards_compat[] __initconst = {
NULL,
};
/* Set system_rev from atags */
static void __init rx51_set_system_rev(const struct tag *tags)
{
const struct tag *tag;
if (tags->hdr.tag != ATAG_CORE)
return;
for_each_tag(tag, tags) {
if (tag->hdr.tag == ATAG_REVISION) {
system_rev = tag->u.revision.rev;
break;
}
}
}
/* Legacy userspace on Nokia N900 needs ATAGS exported in /proc/atags,
* save them while the data is still not overwritten
*/
static void __init rx51_reserve(void)
{
save_atags((const struct tag *)(PAGE_OFFSET + 0x100));
const struct tag *tags = (const struct tag *)(PAGE_OFFSET + 0x100);
save_atags(tags);
rx51_set_system_rev(tags);
omap_reserve();
}

28
arch/arm/mach-omap2/devices.c
View File

@@ -18,7 +18,6 @@
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/mailbox-omap.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
@@ -66,32 +65,6 @@ static int __init omap3_l3_init(void)
}
omap_postcore_initcall(omap3_l3_init);
#if defined(CONFIG_OMAP2PLUS_MBOX) || defined(CONFIG_OMAP2PLUS_MBOX_MODULE)
static inline void __init omap_init_mbox(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
struct omap_mbox_pdata *pdata;
oh = omap_hwmod_lookup("mailbox");
if (!oh) {
pr_err("%s: unable to find hwmod\n", __func__);
return;
}
if (!oh->dev_attr) {
pr_err("%s: hwmod doesn't have valid attrs\n", __func__);
return;
}
pdata = (struct omap_mbox_pdata *)oh->dev_attr;
pdev = omap_device_build("omap-mailbox", -1, oh, pdata, sizeof(*pdata));
WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
__func__, PTR_ERR(pdev));
}
#else
static inline void omap_init_mbox(void) { }
#endif /* CONFIG_OMAP2PLUS_MBOX */
static inline void omap_init_sti(void) {}
#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
@@ -229,7 +202,6 @@ static int __init omap2_init_devices(void)
* please keep these calls, and their implementations above,
* in alphabetical order so they're easier to sort through.
*/
omap_init_mbox();
omap_init_mcspi();
omap_init_sham();
omap_init_aes();

117
arch/arm/mach-omap2/dma.c
View File

@@ -28,6 +28,7 @@
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/of.h>
#include <linux/omap-dma.h>
@@ -203,6 +204,108 @@ static unsigned configure_dma_errata(void)
return errata;
}
static const struct dma_slave_map omap24xx_sdma_map[] = {
{ "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
{ "omap-aes", "tx", SDMA_FILTER_PARAM(9) },
{ "omap-aes", "rx", SDMA_FILTER_PARAM(10) },
{ "omap-sham", "rx", SDMA_FILTER_PARAM(13) },
{ "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
{ "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
{ "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
{ "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
{ "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
{ "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
{ "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
{ "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
{ "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
{ "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
{ "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
{ "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
{ "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
{ "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
{ "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
{ "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
{ "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
{ "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
{ "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
{ "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
{ "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
{ "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
{ "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
{ "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
{ "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
{ "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
{ "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
{ "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
{ "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
{ "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
{ "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
{ "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
{ "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
{ "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
{ "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
{ "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
};
static const struct dma_slave_map omap3xxx_sdma_map[] = {
{ "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
{ "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
{ "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
{ "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
{ "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
{ "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
{ "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
{ "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
{ "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
{ "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
{ "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
{ "omap_i2c.3", "tx", SDMA_FILTER_PARAM(25) },
{ "omap_i2c.3", "rx", SDMA_FILTER_PARAM(26) },
{ "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
{ "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
{ "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
{ "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
{ "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
{ "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
{ "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
{ "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
{ "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
{ "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
{ "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
{ "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
{ "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
{ "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
{ "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
{ "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
{ "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
{ "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
{ "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
{ "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
{ "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
{ "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
{ "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
{ "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
{ "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
{ "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
{ "omap-aes", "tx", SDMA_FILTER_PARAM(65) },
{ "omap-aes", "rx", SDMA_FILTER_PARAM(66) },
{ "omap-sham", "rx", SDMA_FILTER_PARAM(69) },
{ "omap2_mcspi.3", "tx0", SDMA_FILTER_PARAM(70) },
{ "omap2_mcspi.3", "rx0", SDMA_FILTER_PARAM(71) },
{ "omap_hsmmc.2", "tx", SDMA_FILTER_PARAM(77) },
{ "omap_hsmmc.2", "rx", SDMA_FILTER_PARAM(78) },
{ "omap_uart.3", "tx", SDMA_FILTER_PARAM(81) },
{ "omap_uart.3", "rx", SDMA_FILTER_PARAM(82) },
};
static struct omap_system_dma_plat_info dma_plat_info __initdata = {
.reg_map = reg_map,
.channel_stride = 0x60,
@@ -231,6 +334,20 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
p.errata = configure_dma_errata();
if (!of_have_populated_dt()) {
if (soc_is_omap24xx()) {
p.slave_map = omap24xx_sdma_map;
p.slavecnt = ARRAY_SIZE(omap24xx_sdma_map);
} else if (soc_is_omap34xx() || soc_is_omap3630()) {
p.slave_map = omap3xxx_sdma_map;
p.slavecnt = ARRAY_SIZE(omap3xxx_sdma_map);
} else {
pr_err("%s: The legacy DMA map is not provided!\n",
__func__);
return -ENODEV;
}
}
pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
if (IS_ERR(pdev)) {
pr_err("%s: Can't build omap_device for %s:%s.\n",

6
arch/arm/mach-omap2/gpmc-onenand.c
View File

@@ -101,10 +101,8 @@ static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
static void set_onenand_cfg(void __iomem *onenand_base)
{
u32 reg;
u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
ONENAND_SYS_CFG1_BL_16;
if (onenand_flags & ONENAND_FLAG_SYNCREAD)
@@ -123,6 +121,7 @@ static void set_onenand_cfg(void __iomem *onenand_base)
reg |= ONENAND_SYS_CFG1_VHF;
else
reg &= ~ONENAND_SYS_CFG1_VHF;
writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
}
@@ -289,6 +288,7 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
}
}
onenand_async.sync_write = true;
omap2_onenand_calc_async_timings(&t);
ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);

14
arch/arm/mach-omap2/omap_device.c
View File

@@ -191,12 +191,22 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
{
struct platform_device *pdev = to_platform_device(dev);
struct omap_device *od;
int err;
switch (event) {
case BUS_NOTIFY_DEL_DEVICE:
if (pdev->archdata.od)
omap_device_delete(pdev->archdata.od);
break;
case BUS_NOTIFY_UNBOUND_DRIVER:
od = to_omap_device(pdev);
if (od && (od->_state == OMAP_DEVICE_STATE_ENABLED)) {
dev_info(dev, "enabled after unload, idling\n");
err = omap_device_idle(pdev);
if (err)
dev_err(dev, "failed to idle\n");
}
break;
case BUS_NOTIFY_ADD_DEVICE:
if (pdev->dev.of_node)
omap_device_build_from_dt(pdev);
@@ -602,8 +612,10 @@ static int _od_runtime_resume(struct device *dev)
int ret;
ret = omap_device_enable(pdev);
if (ret)
if (ret) {
dev_err(dev, "use pm_runtime_put_sync_suspend() in driver?\n");
return ret;
}
return pm_generic_runtime_resume(dev);
}

17
arch/arm/mach-omap2/omap_hwmod.c
View File

@@ -1416,9 +1416,7 @@ static void _enable_sysc(struct omap_hwmod *oh)
(sf & SYSC_HAS_CLOCKACTIVITY))
_set_clockactivity(oh, oh->class->sysc->clockact, &v);
/* If the cached value is the same as the new value, skip the write */
if (oh->_sysc_cache != v)
_write_sysconfig(v, oh);
_write_sysconfig(v, oh);
/*
* Set the autoidle bit only after setting the smartidle bit
@@ -1481,7 +1479,9 @@ static void _idle_sysc(struct omap_hwmod *oh)
_set_master_standbymode(oh, idlemode, &v);
}
_write_sysconfig(v, oh);
/* If the cached value is the same as the new value, skip the write */
if (oh->_sysc_cache != v)
_write_sysconfig(v, oh);
}
/**
@@ -2200,6 +2200,11 @@ static int _enable(struct omap_hwmod *oh)
*/
static int _idle(struct omap_hwmod *oh)
{
if (oh->flags & HWMOD_NO_IDLE) {
oh->_int_flags |= _HWMOD_SKIP_ENABLE;
return 0;
}
pr_debug("omap_hwmod: %s: idling\n", oh->name);
if (oh->_state != _HWMOD_STATE_ENABLED) {
@@ -2504,6 +2509,8 @@ static int __init _init(struct omap_hwmod *oh, void *data)
oh->flags |= HWMOD_INIT_NO_RESET;
if (of_find_property(np, "ti,no-idle-on-init", NULL))
oh->flags |= HWMOD_INIT_NO_IDLE;
if (of_find_property(np, "ti,no-idle", NULL))
oh->flags |= HWMOD_NO_IDLE;
}
oh->_state = _HWMOD_STATE_INITIALIZED;
@@ -2630,7 +2637,7 @@ static void __init _setup_postsetup(struct omap_hwmod *oh)
* XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data -
* it should be set by the core code as a runtime flag during startup
*/
if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
if ((oh->flags & (HWMOD_INIT_NO_IDLE | HWMOD_NO_IDLE)) &&
(postsetup_state == _HWMOD_STATE_IDLE)) {
oh->_int_flags |= _HWMOD_SKIP_ENABLE;
postsetup_state = _HWMOD_STATE_ENABLED;

3
arch/arm/mach-omap2/omap_hwmod.h
View File

@@ -525,6 +525,8 @@ struct omap_hwmod_omap4_prcm {
* or idled.
* HWMOD_OPT_CLKS_NEEDED: The optional clocks are needed for the module to
* operate and they need to be handled at the same time as the main_clk.
* HWMOD_NO_IDLE: Do not idle the hwmod at all. Useful to handle certain
* IPs like CPSW on DRA7, where clocks to this module cannot be disabled.
*/
#define HWMOD_SWSUP_SIDLE (1 << 0)
#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -541,6 +543,7 @@ struct omap_hwmod_omap4_prcm {
#define HWMOD_SWSUP_SIDLE_ACT (1 << 12)
#define HWMOD_RECONFIG_IO_CHAIN (1 << 13)
#define HWMOD_OPT_CLKS_NEEDED (1 << 14)
#define HWMOD_NO_IDLE (1 << 15)
/*
* omap_hwmod._int_flags definitions

14
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View File

@@ -1020,9 +1020,21 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
NULL,
};
static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_wkup__rtc,
NULL,
};
int __init am43xx_hwmod_init(void)
{
int ret;
omap_hwmod_am43xx_reg();
omap_hwmod_init();
return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
if (!ret && of_machine_is_compatible("ti,am4372"))
ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
return ret;
}

111
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@@ -429,6 +429,67 @@ static struct omap_hwmod dra7xx_dma_system_hwmod = {
.dev_attr = &dma_dev_attr,
};
/*
* 'tpcc' class
*
*/
static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
.name = "tpcc",
};
static struct omap_hwmod dra7xx_tpcc_hwmod = {
.name = "tpcc",
.class = &dra7xx_tpcc_hwmod_class,
.clkdm_name = "l3main1_clkdm",
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
},
},
};
/*
* 'tptc' class
*
*/
static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
.name = "tptc",
};
/* tptc0 */
static struct omap_hwmod dra7xx_tptc0_hwmod = {
.name = "tptc0",
.class = &dra7xx_tptc_hwmod_class,
.clkdm_name = "l3main1_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/* tptc1 */
static struct omap_hwmod dra7xx_tptc1_hwmod = {
.name = "tptc1",
.class = &dra7xx_tptc_hwmod_class,
.clkdm_name = "l3main1_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'dss' class
*
@@ -1526,8 +1587,31 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
*
*/
/*
* As noted in documentation for _reset() in omap_hwmod.c, the stock reset
* functionality of OMAP HWMOD layer does not deassert the hardreset lines
* associated with an IP automatically leaving the driver to handle that
* by itself. This does not work for PCIeSS which needs the reset lines
* deasserted for the driver to start accessing registers.
*
* We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
* lines after asserting them.
*/
static int dra7xx_pciess_reset(struct omap_hwmod *oh)
{
int i;
for (i = 0; i < oh->rst_lines_cnt; i++) {
omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
}
return 0;
}
static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
.name = "pcie",
.reset = dra7xx_pciess_reset,
};
/* pcie1 */
@@ -2563,6 +2647,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> tpcc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_tpcc_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU,
};
/* l3_main_1 -> tptc0 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_tptc0_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU,
};
/* l3_main_1 -> tptc1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_tptc1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
{
.name = "family",
@@ -3380,6 +3488,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__mcasp3,
&dra7xx_gmac__mdio,
&dra7xx_l4_cfg__dma_system,
&dra7xx_l3_main_1__tpcc,
&dra7xx_l3_main_1__tptc0,
&dra7xx_l3_main_1__tptc1,
&dra7xx_l3_main_1__dss,
&dra7xx_l3_main_1__dispc,
&dra7xx_l3_main_1__hdmi,

38
arch/arm/mach-omap2/omap_hwmod_81xx_data.c
View File

@@ -228,6 +228,42 @@ static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
.user = OCP_USER_MPU,
};
/* RTC */
static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = {
.rev_offs = 0x74,
.sysc_offs = 0x78,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = SIDLE_FORCE | SIDLE_NO |
SIDLE_SMART | SIDLE_SMART_WKUP,
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
.name = "rtc",
.sysc = &ti81xx_rtc_sysc,
};
struct omap_hwmod ti81xx_rtc_hwmod = {
.name = "rtc",
.class = &ti81xx_rtc_hwmod_class,
.clkdm_name = "alwon_l3s_clkdm",
.flags = HWMOD_NO_IDLEST,
.main_clk = "sysclk18_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &ti81xx_rtc_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
/* UART common */
static struct omap_hwmod_class_sysconfig uart_sysc = {
.rev_offs = 0x50,
@@ -1383,6 +1419,7 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_l4_ls__mcspi1,
&dm814x_l4_ls__mmc1,
&dm814x_l4_ls__mmc2,
&ti81xx_l4_ls__rtc,
&dm81xx_alwon_l3_fast__tpcc,
&dm81xx_alwon_l3_fast__tptc0,
&dm81xx_alwon_l3_fast__tptc1,
@@ -1422,6 +1459,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_l4_ls__gpio1,
&dm81xx_l4_ls__gpio2,
&dm81xx_l4_ls__elm,
&ti81xx_l4_ls__rtc,
&dm816x_l4_ls__mmc1,
&dm816x_l4_ls__timer1,
&dm816x_l4_ls__timer2,

23
arch/arm/mach-omap2/pdata-quirks.c
View File

@@ -23,6 +23,8 @@
#include <linux/platform_data/pinctrl-single.h>
#include <linux/platform_data/iommu-omap.h>
#include <linux/platform_data/wkup_m3.h>
#include <linux/platform_data/pwm_omap_dmtimer.h>
#include <plat/dmtimer.h>
#include "common.h"
#include "common-board-devices.h"
@@ -449,6 +451,24 @@ void omap_auxdata_legacy_init(struct device *dev)
dev->platform_data = &twl_gpio_auxdata;
}
/* Dual mode timer PWM callbacks platdata */
#if IS_ENABLED(CONFIG_OMAP_DM_TIMER)
struct pwm_omap_dmtimer_pdata pwm_dmtimer_pdata = {
.request_by_node = omap_dm_timer_request_by_node,
.free = omap_dm_timer_free,
.enable = omap_dm_timer_enable,
.disable = omap_dm_timer_disable,
.get_fclk = omap_dm_timer_get_fclk,
.start = omap_dm_timer_start,
.stop = omap_dm_timer_stop,
.set_load = omap_dm_timer_set_load,
.set_match = omap_dm_timer_set_match,
.set_pwm = omap_dm_timer_set_pwm,
.set_prescaler = omap_dm_timer_set_prescaler,
.write_counter = omap_dm_timer_write_counter,
};
#endif
/*
* Few boards still need auxdata populated before we populate
* the dev entries in of_platform_populate().
@@ -502,6 +522,9 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3",
&wkup_m3_data),
#endif
#if IS_ENABLED(CONFIG_OMAP_DM_TIMER)
OF_DEV_AUXDATA("ti,omap-dmtimer-pwm", 0, NULL, &pwm_dmtimer_pdata),
#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu",
&omap4_iommu_pdata),

2
arch/arm/mach-omap2/serial.c
View File

@@ -252,7 +252,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
info = omap_serial_default_info;
oh = uart->oh;
name = DRIVER_NAME;
name = OMAP_SERIAL_DRIVER_NAME;
omap_up.dma_enabled = info->dma_enabled;
omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;

61
arch/arm/mach-omap2/sleep34xx.S
View File

@@ -86,13 +86,18 @@ ENTRY(enable_omap3630_toggle_l2_on_restore)
stmfd sp!, {lr} @ save registers on stack
/* Setup so that we will disable and enable l2 */
mov r1, #0x1
adrl r2, l2dis_3630 @ may be too distant for plain adr
str r1, [r2]
adrl r3, l2dis_3630_offset @ may be too distant for plain adr
ldr r2, [r3] @ value for offset
str r1, [r2, r3] @ write to l2dis_3630
ldmfd sp!, {pc} @ restore regs and return
ENDPROC(enable_omap3630_toggle_l2_on_restore)
.text
/* Function to call rom code to save secure ram context */
/*
* Function to call rom code to save secure ram context. This gets
* relocated to SRAM, so it can be all in .data section. Otherwise
* we need to initialize api_params separately.
*/
.data
.align 3
ENTRY(save_secure_ram_context)
stmfd sp!, {r4 - r11, lr} @ save registers on stack
@@ -126,6 +131,8 @@ ENDPROC(save_secure_ram_context)
ENTRY(save_secure_ram_context_sz)
.word . - save_secure_ram_context
.text
/*
* ======================
* == Idle entry point ==
@@ -289,12 +296,6 @@ wait_sdrc_ready:
bic r5, r5, #0x40
str r5, [r4]
/*
* PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a
* base instead.
* Be careful not to clobber r7 when maintaing this code.
*/
is_dll_in_lock_mode:
/* Is dll in lock mode? */
ldr r4, sdrc_dlla_ctrl
@@ -302,11 +303,7 @@ is_dll_in_lock_mode:
tst r5, #0x4
bne exit_nonoff_modes @ Return if locked
/* wait till dll locks */
adr r7, kick_counter
wait_dll_lock_timed:
ldr r4, wait_dll_lock_counter
add r4, r4, #1
str r4, [r7, #wait_dll_lock_counter - kick_counter]
ldr r4, sdrc_dlla_status
/* Wait 20uS for lock */
mov r6, #8
@@ -330,9 +327,6 @@ kick_dll:
orr r6, r6, #(1<<3) @ enable dll
str r6, [r4]
dsb
ldr r4, kick_counter
add r4, r4, #1
str r4, [r7] @ kick_counter
b wait_dll_lock_timed
exit_nonoff_modes:
@@ -360,15 +354,6 @@ sdrc_dlla_status:
.word SDRC_DLLA_STATUS_V
sdrc_dlla_ctrl:
.word SDRC_DLLA_CTRL_V
/*
* When exporting to userspace while the counters are in SRAM,
* these 2 words need to be at the end to facilitate retrival!
*/
kick_counter:
.word 0
wait_dll_lock_counter:
.word 0
ENTRY(omap3_do_wfi_sz)
.word . - omap3_do_wfi
@@ -437,7 +422,9 @@ ENTRY(omap3_restore)
cmp r2, #0x0 @ Check if target power state was OFF or RET
bne logic_l1_restore
ldr r0, l2dis_3630
adr r1, l2dis_3630_offset @ address for offset
ldr r0, [r1] @ value for offset
ldr r0, [r1, r0] @ value at l2dis_3630
cmp r0, #0x1 @ should we disable L2 on 3630?
bne skipl2dis
mrc p15, 0, r0, c1, c0, 1
@@ -449,12 +436,14 @@ skipl2dis:
and r1, #0x700
cmp r1, #0x300
beq l2_inv_gp
adr r0, l2_inv_api_params_offset
ldr r3, [r0]
add r3, r3, r0 @ r3 points to dummy parameters
mov r0, #40 @ set service ID for PPA
mov r12, r0 @ copy secure Service ID in r12
mov r1, #0 @ set task id for ROM code in r1
mov r2, #4 @ set some flags in r2, r6
mov r6, #0xff
adr r3, l2_inv_api_params @ r3 points to dummy parameters
dsb @ data write barrier
dmb @ data memory barrier
smc #1 @ call SMI monitor (smi #1)
@@ -488,8 +477,8 @@ skipl2dis:
b logic_l1_restore
.align
l2_inv_api_params:
.word 0x1, 0x00
l2_inv_api_params_offset:
.long l2_inv_api_params - .
l2_inv_gp:
/* Execute smi to invalidate L2 cache */
mov r12, #0x1 @ set up to invalidate L2
@@ -506,7 +495,9 @@ l2_inv_gp:
mov r12, #0x2
smc #0 @ Call SMI monitor (smieq)
logic_l1_restore:
ldr r1, l2dis_3630
adr r0, l2dis_3630_offset @ adress for offset
ldr r1, [r0] @ value for offset
ldr r1, [r0, r1] @ value at l2dis_3630
cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
bne skipl2reen
mrc p15, 0, r1, c1, c0, 1
@@ -535,9 +526,17 @@ control_stat:
.word CONTROL_STAT
control_mem_rta:
.word CONTROL_MEM_RTA_CTRL
l2dis_3630_offset:
.long l2dis_3630 - .
.data
l2dis_3630:
.word 0
.data
l2_inv_api_params:
.word 0x1, 0x00
/*
* Internal functions
*/

25
arch/arm/mach-omap2/sleep44xx.S
View File

@@ -29,12 +29,6 @@
dsb
.endm
ppa_zero_params:
.word 0x0
ppa_por_params:
.word 1, 0
#ifdef CONFIG_ARCH_OMAP4
/*
@@ -266,7 +260,9 @@ ENTRY(omap4_cpu_resume)
beq skip_ns_smp_enable
ppa_actrl_retry:
mov r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX
adr r3, ppa_zero_params @ Pointer to parameters
adr r1, ppa_zero_params_offset
ldr r3, [r1]
add r3, r3, r1 @ Pointer to ppa_zero_params
mov r1, #0x0 @ Process ID
mov r2, #0x4 @ Flag
mov r6, #0xff
@@ -303,7 +299,9 @@ skip_ns_smp_enable:
ldr r0, =OMAP4_PPA_L2_POR_INDEX
ldr r1, =OMAP44XX_SAR_RAM_BASE
ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
adr r3, ppa_por_params
adr r1, ppa_por_params_offset
ldr r3, [r1]
add r3, r3, r1 @ Pointer to ppa_por_params
str r4, [r3, #0x04]
mov r1, #0x0 @ Process ID
mov r2, #0x4 @ Flag
@@ -328,6 +326,8 @@ skip_l2en:
#endif
b cpu_resume @ Jump to generic resume
ppa_por_params_offset:
.long ppa_por_params - .
ENDPROC(omap4_cpu_resume)
#endif /* CONFIG_ARCH_OMAP4 */
@@ -380,4 +380,13 @@ ENTRY(omap_do_wfi)
nop
ldmfd sp!, {pc}
ppa_zero_params_offset:
.long ppa_zero_params - .
ENDPROC(omap_do_wfi)
.data
ppa_zero_params:
.word 0
ppa_por_params:
.word 1, 0

23
arch/arm/mach-omap2/soc.h
View File

@@ -181,6 +181,14 @@ static inline int is_ti ##class (void) \
return (GET_TI_CLASS == (id)) ? 1 : 0; \
}
#define GET_DRA_CLASS ((omap_rev() >> 24) & 0xff)
#define IS_DRA_CLASS(class, id) \
static inline int is_dra ##class (void) \
{ \
return (GET_DRA_CLASS == (id)) ? 1 : 0; \
}
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
#define IS_OMAP_SUBCLASS(subclass, id) \
@@ -201,6 +209,12 @@ static inline int is_am ##subclass (void) \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
#define IS_DRA_SUBCLASS(subclass, id) \
static inline int is_dra ##subclass (void) \
{ \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
@@ -210,6 +224,7 @@ IS_AM_CLASS(33xx, 0x33)
IS_AM_CLASS(43xx, 0x43)
IS_TI_CLASS(81xx, 0x81)
IS_DRA_CLASS(7xx, 0x7)
IS_OMAP_SUBCLASS(242x, 0x242)
IS_OMAP_SUBCLASS(243x, 0x243)
@@ -224,6 +239,8 @@ IS_TI_SUBCLASS(816x, 0x816)
IS_TI_SUBCLASS(814x, 0x814)
IS_AM_SUBCLASS(335x, 0x335)
IS_AM_SUBCLASS(437x, 0x437)
IS_DRA_SUBCLASS(75x, 0x75)
IS_DRA_SUBCLASS(72x, 0x72)
#define soc_is_omap24xx() 0
#define soc_is_omap242x() 0
@@ -397,9 +414,9 @@ IS_OMAP_TYPE(3430, 0x3430)
#undef soc_is_dra7xx
#undef soc_is_dra74x
#undef soc_is_dra72x
#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
#define soc_is_dra74x() (of_machine_is_compatible("ti,dra74"))
#define soc_is_dra72x() (of_machine_is_compatible("ti,dra72"))
#define soc_is_dra7xx() is_dra7xx()
#define soc_is_dra74x() is_dra75x()
#define soc_is_dra72x() is_dra72x()
#endif
/* Various silicon revisions for omap2 */