ARM: proc-v7: move CPU errata out of line
Rather than having a long sprawling __v7_setup function, which is hard to maintain properly, move the CPU errata out of line. While doing this, it was discovered that the Cortex-A15 errata had been incorrectly added: ldr r10, =0x00000c08 @ Cortex-A8 primary part number teq r0, r10 bne 2f /* Cortex-A8 errata */ b 3f 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number teq r0, r10 bne 3f /* Cortex-A9 errata */ 3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number teq r0, r10 bne 4f /* Cortex-A15 errata */ 4: This results in the Cortex-A15 test always being executed after the Cortex-A8 and Cortex-A9 errata, which is obviously not what is intended. The 'b 3f' labels should have been updated to 'b 4f'. The new structure of: /* Cortex-A8 Errata */ ldr r10, =0x00000c08 @ Cortex-A8 primary part number teq r0, r10 beq __ca8_errata /* Cortex-A9 Errata */ ldr r10, =0x00000c09 @ Cortex-A9 primary part number teq r0, r10 beq __ca9_errata /* Cortex-A15 Errata */ ldr r10, =0x00000c0f @ Cortex-A15 primary part number teq r0, r10 beq __ca15_errata __errata_finish: is much cleaner and easier to see that this kind of thing doesn't happen. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
@@ -252,6 +252,12 @@ ENDPROC(cpu_pj4b_do_resume)
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* Initialise TLB, Caches, and MMU state ready to switch the MMU
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* Initialise TLB, Caches, and MMU state ready to switch the MMU
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* on. Return in r0 the new CP15 C1 control register setting.
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* on. Return in r0 the new CP15 C1 control register setting.
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*
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*
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* r1, r2, r4, r5, r9 must be preserved.
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* r4: TTBR0 (low word)
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* r5: TTBR0 (high word if LPAE)
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* r8: TTBR1
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* r9: Main ID register
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*
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* This should be able to cover all ARMv7 cores.
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* This should be able to cover all ARMv7 cores.
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*
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*
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* It is assumed that:
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* It is assumed that:
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@@ -279,6 +285,70 @@ __v7_ca17mp_setup:
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#endif
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#endif
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b __v7_setup
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b __v7_setup
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__ca8_errata:
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#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
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teq r3, #0x00100000 @ only present in r1p*
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 6) @ set IBE to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_458693
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teq r6, #0x20 @ only present in r2p0
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 5) @ set L1NEON to 1
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orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_460075
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teq r6, #0x20 @ only present in r2p0
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mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
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tsteq r10, #1 << 22
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orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
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mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
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#endif
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b __errata_finish
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__ca9_errata:
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#ifdef CONFIG_ARM_ERRATA_742230
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cmp r6, #0x22 @ only present up to r2p2
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mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orrle r10, r10, #1 << 4 @ set bit #4
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mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_742231
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teq r6, #0x20 @ present in r2p0
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teqne r6, #0x21 @ present in r2p1
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teqne r6, #0x22 @ present in r2p2
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mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orreq r10, r10, #1 << 12 @ set bit #12
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orreq r10, r10, #1 << 22 @ set bit #22
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_743622
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teq r3, #0x00200000 @ only present in r2p*
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mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orreq r10, r10, #1 << 6 @ set bit #6
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
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ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
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ALT_UP_B(1f)
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mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orrlt r10, r10, #1 << 11 @ set bit #11
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mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
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1:
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#endif
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b __errata_finish
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__ca15_errata:
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#ifdef CONFIG_ARM_ERRATA_773022
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cmp r6, #0x4 @ only present up to r0p4
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mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
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orrle r10, r10, #1 << 1 @ disable loop buffer
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mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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b __errata_finish
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__v7_pj4b_setup:
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__v7_pj4b_setup:
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#ifdef CONFIG_CPU_PJ4B
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#ifdef CONFIG_CPU_PJ4B
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@@ -342,7 +412,7 @@ __v7_setup:
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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and r10, r0, #0xff000000 @ ARM?
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and r10, r0, #0xff000000 @ ARM?
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teq r10, #0x41000000
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teq r10, #0x41000000
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bne 3f
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bne __errata_finish
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and r3, r0, #0x00f00000 @ variant
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and r3, r0, #0x00f00000 @ variant
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and r6, r0, #0x0000000f @ revision
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and r6, r0, #0x0000000f @ revision
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orr r6, r6, r3, lsr #20-4 @ combine variant and revision
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orr r6, r6, r3, lsr #20-4 @ combine variant and revision
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@@ -351,77 +421,20 @@ __v7_setup:
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/* Cortex-A8 Errata */
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/* Cortex-A8 Errata */
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ldr r10, =0x00000c08 @ Cortex-A8 primary part number
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ldr r10, =0x00000c08 @ Cortex-A8 primary part number
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teq r0, r10
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teq r0, r10
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bne 2f
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beq __ca8_errata
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#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
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teq r3, #0x00100000 @ only present in r1p*
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 6) @ set IBE to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_458693
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teq r6, #0x20 @ only present in r2p0
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 5) @ set L1NEON to 1
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orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_460075
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teq r6, #0x20 @ only present in r2p0
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mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
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tsteq r10, #1 << 22
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orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
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mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
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#endif
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b 3f
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/* Cortex-A9 Errata */
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/* Cortex-A9 Errata */
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2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
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ldr r10, =0x00000c09 @ Cortex-A9 primary part number
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teq r0, r10
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teq r0, r10
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bne 3f
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beq __ca9_errata
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#ifdef CONFIG_ARM_ERRATA_742230
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cmp r6, #0x22 @ only present up to r2p2
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mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orrle r10, r10, #1 << 4 @ set bit #4
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mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_742231
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teq r6, #0x20 @ present in r2p0
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teqne r6, #0x21 @ present in r2p1
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teqne r6, #0x22 @ present in r2p2
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mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orreq r10, r10, #1 << 12 @ set bit #12
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orreq r10, r10, #1 << 22 @ set bit #22
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_743622
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teq r3, #0x00200000 @ only present in r2p*
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mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orreq r10, r10, #1 << 6 @ set bit #6
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
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ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
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ALT_UP_B(1f)
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mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orrlt r10, r10, #1 << 11 @ set bit #11
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mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
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1:
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#endif
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/* Cortex-A15 Errata */
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/* Cortex-A15 Errata */
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3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
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ldr r10, =0x00000c0f @ Cortex-A15 primary part number
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teq r0, r10
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teq r0, r10
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bne 4f
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beq __ca15_errata
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#ifdef CONFIG_ARM_ERRATA_773022
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__errata_finish:
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cmp r6, #0x4 @ only present up to r0p4
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mov r10, #0
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mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
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orrle r10, r10, #1 << 1 @ disable loop buffer
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mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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4: mov r10, #0
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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#ifdef CONFIG_MMU
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#ifdef CONFIG_MMU
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mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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