Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner: "This updated pull request does not contain the last few GIC related patches which were reported to cause a regression. There is a fix available, but I let it breed for a couple of days first. The irq departement provides: - new infrastructure to support non PCI based MSI interrupts - a couple of new irq chip drivers - the usual pile of fixlets and updates to irq chip drivers - preparatory changes for removal of the irq argument from interrupt flow handlers - preparatory changes to remove IRQF_VALID" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (129 commits) irqchip/imx-gpcv2: IMX GPCv2 driver for wakeup sources irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2 irqchip: Add documentation for the bcm2836 interrupt controller irqchip/bcm2835: Add support for being used as a second level controller irqchip/bcm2835: Refactor handle_IRQ() calls out of MAKE_HWIRQ PCI: xilinx: Fix typo in function name irqchip/gic: Ensure gic_cpu_if_up/down() programs correct GIC instance irqchip/gic: Only allow the primary GIC to set the CPU map PCI/MSI: pci-xgene-msi: Consolidate chained IRQ handler install/remove unicore32/irq: Prepare puv3_gpio_handler for irq argument removal tile/pci_gx: Prepare trio_handle_level_irq for irq argument removal m68k/irq: Prepare irq handlers for irq argument removal C6X/megamode-pic: Prepare megamod_irq_cascade for irq argument removal blackfin: Prepare irq handlers for irq argument removal arc/irq: Prepare idu_cascade_isr for irq argument removal sparc/irq: Use access helper irq_data_get_affinity_mask() sparc/irq: Use helper irq_data_get_irq_handler_data() parisc/irq: Use access helper irq_data_get_affinity_mask() mn10300/irq: Use access helper irq_data_get_affinity_mask() irqchip/i8259: Prepare i8259_irq_dispatch for irq argument removal ...
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@@ -304,11 +304,12 @@ static struct irq_chip tilegx_legacy_irq_chip = {
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* to Linux which just calls handle_level_irq() after clearing the
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* MAC INTx Assert status bit associated with this interrupt.
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*/
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static void trio_handle_level_irq(unsigned int irq, struct irq_desc *desc)
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static void trio_handle_level_irq(unsigned int __irq, struct irq_desc *desc)
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{
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struct pci_controller *controller = irq_desc_get_handler_data(desc);
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gxio_trio_context_t *trio_context = controller->trio;
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uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc);
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unsigned int irq = irq_desc_get_irq(desc);
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int mac = controller->mac;
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unsigned int reg_offset;
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uint64_t level_mask;
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@@ -1442,7 +1443,7 @@ static struct pci_ops tile_cfg_ops = {
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/* MSI support starts here. */
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static unsigned int tilegx_msi_startup(struct irq_data *d)
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{
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if (d->msi_desc)
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if (irq_data_get_msi_desc(d))
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pci_msi_unmask_irq(d);
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return 0;
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