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RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}

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These are just hard coded in the RISC-V port, which doesn't make any
sense.  We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.

Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Palmer Dabbelt
2018-07-24 17:17:14 -07:00
parent 84df9525b0
commit 1760debb51
1 changed files with 0 additions and 7 deletions
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7
arch/riscv/kernel/cacheinfo.c
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@@ -22,13 +22,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
{ {
this_leaf->level = level; this_leaf->level = level;
this_leaf->type = type; this_leaf->type = type;
/* not a sector cache */
this_leaf->physical_line_partition = 1;
/* TODO: Add to DTS */
this_leaf->attributes =
CACHE_WRITE_BACK
| CACHE_READ_ALLOCATE
| CACHE_WRITE_ALLOCATE;
} }
static int __init_cache_level(unsigned int cpu) static int __init_cache_level(unsigned int cpu)