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MIPS: Octeon: Changes to support readq()/writeq() usage.

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Update OCTEON port mangling code to support readq() and
writeq() functions to allow driver code to be more portable.
Updates also for word and long function pairs. We also
remove SWAP_IO_SPACE for OCTEON platforms as the function
macros are redundant with the new mangling code.

Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Acked-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13780/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Steven J. Hill
2016-07-08 21:45:01 -05:00
committed by Ralf Baechle
parent acd168c0bf
commit 1685ddbe35
3 changed files with 32 additions and 31 deletions
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20
arch/mips/cavium-octeon/setup.c
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@@ -40,9 +40,27 @@
#include <asm/octeon/octeon.h>
#include <asm/octeon/pci-octeon.h>
#include <asm/octeon/cvmx-mio-defs.h>
#include <asm/octeon/cvmx-rst-defs.h>
/*
* TRUE for devices having registers with little-endian byte
* order, FALSE for registers with native-endian byte order.
* PCI mandates little-endian, USB and SATA are configuraable,
* but we chose little-endian for these.
*/
const bool octeon_should_swizzle_table[256] = {
[0x00] = true, /* bootbus/CF */
[0x1b] = true, /* PCI mmio window */
[0x1c] = true, /* PCI mmio window */
[0x1d] = true, /* PCI mmio window */
[0x1e] = true, /* PCI mmio window */
[0x68] = true, /* OCTEON III USB */
[0x69] = true, /* OCTEON III USB */
[0x6c] = true, /* OCTEON III SATA */
[0x6f] = true, /* OCTEON II USB */
};
EXPORT_SYMBOL(octeon_should_swizzle_table);
#ifdef CONFIG_PCI
extern void pci_console_init(const char *arg);
#endif