Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Arnd Bergmann: "This release brings up a new platform based on the old ARM9 core: the Nuvoton NPCM is used as a baseboard management controller, competing with the better known ASpeed AST2xx series. Another important change is the addition of ARMv7-A based chips in mach-stm32. The older parts in this platform are ARMv7-M based microcontrollers, now they are expanding to general-purpose workloads. The other changes are the usual defconfig updates to enable additional drivers, lesser bugfixes. The largest updates as often are the ongoing OMAP cleanups, but we also have a number of changes for the older PXA and davinci platforms this time. For the Renesas shmobile/r-car platform, some new infrastructure is needed to make the watchdog work correctly. Supporting Multiprocessing on Allwinner A80 required a significant amount of new code, but is not doing anything unexpected" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (179 commits) arm: npcm: modify configuration for the NPCM7xx BMC. MAINTAINERS: update entry for ARM/berlin ARM: omap2: fix am43xx build without L2X0 ARM: davinci: da8xx: simplify CFGCHIP regmap_config ARM: davinci: da8xx: fix oops in USB PHY driver due to stack allocated platform_data ARM: multi_v7_defconfig: add NXP FlexCAN IP support ARM: multi_v7_defconfig: enable thermal driver for i.MX devices ARM: multi_v7_defconfig: add RN5T618 PMIC family support ARM: multi_v7_defconfig: add NXP graphics drivers ARM: multi_v7_defconfig: add GPMI NAND controller support ARM: multi_v7_defconfig: add OCOTP driver for NXP SoCs ARM: multi_v7_defconfig: configure I2C driver built-in arm64: defconfig: add CONFIG_UNIPHIER_THERMAL and CONFIG_SNI_AVE ARM: imx: fix imx6sll-only build ARM: imx: select ARM_CPU_SUSPEND for CPU_IDLE as well ARM: mxs_defconfig: Re-sync defconfig ARM: imx_v4_v5_defconfig: Use the generic fsl-asoc-card driver ARM: imx_v4_v5_defconfig: Re-sync defconfig arm64: defconfig: enable stmmac ethernet to defconfig ARM: EXYNOS: Simplify code in coupled CPU idle hot path ...
This commit is contained in:
Linus Torvalds
394
include/clocksource/timer-ti-dm.h
Normal file
394
include/clocksource/timer-ti-dm.h
Normal file
@@ -0,0 +1,394 @@
|
||||
/*
|
||||
* OMAP Dual-Mode Timers
|
||||
*
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||||
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Tarun Kanti DebBarma <tarun.kanti@ti.com>
|
||||
* Thara Gopinath <thara@ti.com>
|
||||
*
|
||||
* Platform device conversion and hwmod support.
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
* Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
|
||||
* PWM and clock framwork support by Timo Teras.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
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||||
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||||
#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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||||
#ifndef __CLOCKSOURCE_DMTIMER_H
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#define __CLOCKSOURCE_DMTIMER_H
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/* clock sources */
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#define OMAP_TIMER_SRC_SYS_CLK 0x00
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#define OMAP_TIMER_SRC_32_KHZ 0x01
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#define OMAP_TIMER_SRC_EXT_CLK 0x02
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/* timer interrupt enable bits */
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#define OMAP_TIMER_INT_CAPTURE (1 << 2)
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#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
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#define OMAP_TIMER_INT_MATCH (1 << 0)
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/* trigger types */
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#define OMAP_TIMER_TRIGGER_NONE 0x00
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#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
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#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
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/* posted mode types */
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#define OMAP_TIMER_NONPOSTED 0x00
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#define OMAP_TIMER_POSTED 0x01
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/* timer capabilities used in hwmod database */
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#define OMAP_TIMER_SECURE 0x80000000
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#define OMAP_TIMER_ALWON 0x40000000
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#define OMAP_TIMER_HAS_PWM 0x20000000
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#define OMAP_TIMER_NEEDS_RESET 0x10000000
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#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
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|
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/*
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* timer errata flags
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*
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||||
* Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
|
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* errata prevents us from using posted mode on these devices, unless the
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* timer counter register is never read. For more details please refer to
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* the OMAP3/4/5 errata documents.
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*/
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#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
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struct timer_regs {
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u32 tidr;
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u32 tier;
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u32 twer;
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u32 tclr;
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u32 tcrr;
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u32 tldr;
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u32 ttrg;
|
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u32 twps;
|
||||
u32 tmar;
|
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u32 tcar1;
|
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u32 tsicr;
|
||||
u32 tcar2;
|
||||
u32 tpir;
|
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u32 tnir;
|
||||
u32 tcvr;
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u32 tocr;
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u32 towr;
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||||
};
|
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|
||||
struct omap_dm_timer {
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||||
int id;
|
||||
int irq;
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struct clk *fclk;
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|
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void __iomem *io_base;
|
||||
void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
|
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void __iomem *irq_ena; /* irq enable */
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void __iomem *irq_dis; /* irq disable, only on v2 ip */
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||||
void __iomem *pend; /* write pending */
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void __iomem *func_base; /* function register base */
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||||
|
||||
unsigned long rate;
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||||
unsigned reserved:1;
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||||
unsigned posted:1;
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||||
struct timer_regs context;
|
||||
int (*get_context_loss_count)(struct device *);
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||||
int ctx_loss_count;
|
||||
int revision;
|
||||
u32 capability;
|
||||
u32 errata;
|
||||
struct platform_device *pdev;
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||||
struct list_head node;
|
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};
|
||||
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||||
int omap_dm_timer_reserve_systimer(int id);
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struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
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||||
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int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
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||||
|
||||
u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
|
||||
|
||||
int omap_dm_timer_trigger(struct omap_dm_timer *timer);
|
||||
|
||||
int omap_dm_timers_active(void);
|
||||
|
||||
/*
|
||||
* Do not use the defines below, they are not needed. They should be only
|
||||
* used by dmtimer.c and sys_timer related code.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The interrupt registers are different between v1 and v2 ip.
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||||
* These registers are offsets from timer->iobase.
|
||||
*/
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||||
#define OMAP_TIMER_ID_OFFSET 0x00
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||||
#define OMAP_TIMER_OCP_CFG_OFFSET 0x10
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||||
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||||
#define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14
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||||
#define OMAP_TIMER_V1_STAT_OFFSET 0x18
|
||||
#define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c
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||||
|
||||
#define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24
|
||||
#define OMAP_TIMER_V2_IRQSTATUS 0x28
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||||
#define OMAP_TIMER_V2_IRQENABLE_SET 0x2c
|
||||
#define OMAP_TIMER_V2_IRQENABLE_CLR 0x30
|
||||
|
||||
/*
|
||||
* The functional registers have a different base on v1 and v2 ip.
|
||||
* These registers are offsets from timer->func_base. The func_base
|
||||
* is samae as io_base for v1 and io_base + 0x14 for v2 ip.
|
||||
*
|
||||
*/
|
||||
#define OMAP_TIMER_V2_FUNC_OFFSET 0x14
|
||||
|
||||
#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
|
||||
#define _OMAP_TIMER_CTRL_OFFSET 0x24
|
||||
#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
|
||||
#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
|
||||
#define OMAP_TIMER_CTRL_PT (1 << 12)
|
||||
#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
|
||||
#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
|
||||
#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
|
||||
#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
|
||||
#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
|
||||
#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
|
||||
#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
|
||||
#define OMAP_TIMER_CTRL_POSTED (1 << 2)
|
||||
#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
|
||||
#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
|
||||
#define _OMAP_TIMER_COUNTER_OFFSET 0x28
|
||||
#define _OMAP_TIMER_LOAD_OFFSET 0x2c
|
||||
#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
|
||||
#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
|
||||
#define WP_NONE 0 /* no write pending bit */
|
||||
#define WP_TCLR (1 << 0)
|
||||
#define WP_TCRR (1 << 1)
|
||||
#define WP_TLDR (1 << 2)
|
||||
#define WP_TTGR (1 << 3)
|
||||
#define WP_TMAR (1 << 4)
|
||||
#define WP_TPIR (1 << 5)
|
||||
#define WP_TNIR (1 << 6)
|
||||
#define WP_TCVR (1 << 7)
|
||||
#define WP_TOCR (1 << 8)
|
||||
#define WP_TOWR (1 << 9)
|
||||
#define _OMAP_TIMER_MATCH_OFFSET 0x38
|
||||
#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
|
||||
#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
|
||||
#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
|
||||
#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
|
||||
#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
|
||||
#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
|
||||
#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
|
||||
#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
|
||||
|
||||
/* register offsets with the write pending bit encoded */
|
||||
#define WPSHIFT 16
|
||||
|
||||
#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
|
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| (WP_NONE << WPSHIFT))
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||||
|
||||
#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
|
||||
| (WP_TCLR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
|
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| (WP_TCRR << WPSHIFT))
|
||||
|
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#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
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| (WP_TLDR << WPSHIFT))
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||||
|
||||
#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
|
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| (WP_TTGR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
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| (WP_NONE << WPSHIFT))
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||||
|
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#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
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||||
| (WP_TMAR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
|
||||
| (WP_NONE << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
|
||||
| (WP_NONE << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
|
||||
| (WP_NONE << WPSHIFT))
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||||
|
||||
#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
|
||||
| (WP_TPIR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
|
||||
| (WP_TNIR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
|
||||
| (WP_TCVR << WPSHIFT))
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||||
|
||||
#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
|
||||
(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
|
||||
|
||||
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
|
||||
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
|
||||
|
||||
/*
|
||||
* The below are inlined to optimize code size for system timers. Other code
|
||||
* should not need these at all, see
|
||||
* include/linux/platform_data/pwm_omap_dmtimer.h
|
||||
*/
|
||||
#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2PLUS)
|
||||
static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
|
||||
int posted)
|
||||
{
|
||||
if (posted)
|
||||
while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
|
||||
cpu_relax();
|
||||
|
||||
return readl_relaxed(timer->func_base + (reg & 0xff));
|
||||
}
|
||||
|
||||
static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
|
||||
u32 reg, u32 val, int posted)
|
||||
{
|
||||
if (posted)
|
||||
while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
|
||||
cpu_relax();
|
||||
|
||||
writel_relaxed(val, timer->func_base + (reg & 0xff));
|
||||
}
|
||||
|
||||
static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
|
||||
{
|
||||
u32 tidr;
|
||||
|
||||
/* Assume v1 ip if bits [31:16] are zero */
|
||||
tidr = readl_relaxed(timer->io_base);
|
||||
if (!(tidr >> 16)) {
|
||||
timer->revision = 1;
|
||||
timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
|
||||
timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
|
||||
timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
|
||||
timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
|
||||
timer->func_base = timer->io_base;
|
||||
} else {
|
||||
timer->revision = 2;
|
||||
timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
|
||||
timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
|
||||
timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
|
||||
timer->pend = timer->io_base +
|
||||
_OMAP_TIMER_WRITE_PEND_OFFSET +
|
||||
OMAP_TIMER_V2_FUNC_OFFSET;
|
||||
timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* __omap_dm_timer_enable_posted - enables write posted mode
|
||||
* @timer: pointer to timer instance handle
|
||||
*
|
||||
* Enables the write posted mode for the timer. When posted mode is enabled
|
||||
* writes to certain timer registers are immediately acknowledged by the
|
||||
* internal bus and hence prevents stalling the CPU waiting for the write to
|
||||
* complete. Enabling this feature can improve performance for writing to the
|
||||
* timer registers.
|
||||
*/
|
||||
static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
|
||||
{
|
||||
if (timer->posted)
|
||||
return;
|
||||
|
||||
if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
|
||||
timer->posted = OMAP_TIMER_NONPOSTED;
|
||||
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
|
||||
return;
|
||||
}
|
||||
|
||||
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
|
||||
OMAP_TIMER_CTRL_POSTED, 0);
|
||||
timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
|
||||
timer->posted = OMAP_TIMER_POSTED;
|
||||
}
|
||||
|
||||
/**
|
||||
* __omap_dm_timer_override_errata - override errata flags for a timer
|
||||
* @timer: pointer to timer handle
|
||||
* @errata: errata flags to be ignored
|
||||
*
|
||||
* For a given timer, override a timer errata by clearing the flags
|
||||
* specified by the errata argument. A specific erratum should only be
|
||||
* overridden for a timer if the timer is used in such a way the erratum
|
||||
* has no impact.
|
||||
*/
|
||||
static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
|
||||
u32 errata)
|
||||
{
|
||||
timer->errata &= ~errata;
|
||||
}
|
||||
|
||||
static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
|
||||
int posted, unsigned long rate)
|
||||
{
|
||||
u32 l;
|
||||
|
||||
l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
|
||||
if (l & OMAP_TIMER_CTRL_ST) {
|
||||
l &= ~0x1;
|
||||
__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
|
||||
#ifdef CONFIG_ARCH_OMAP2PLUS
|
||||
/* Readback to make sure write has completed */
|
||||
__omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
|
||||
/*
|
||||
* Wait for functional clock period x 3.5 to make sure that
|
||||
* timer is stopped
|
||||
*/
|
||||
udelay(3500000 / rate + 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Ack possibly pending interrupt */
|
||||
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
|
||||
}
|
||||
|
||||
static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
|
||||
u32 ctrl, unsigned int load,
|
||||
int posted)
|
||||
{
|
||||
__omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
|
||||
__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
|
||||
}
|
||||
|
||||
static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
|
||||
unsigned int value)
|
||||
{
|
||||
writel_relaxed(value, timer->irq_ena);
|
||||
__omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
|
||||
}
|
||||
|
||||
static inline unsigned int
|
||||
__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
|
||||
{
|
||||
return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
|
||||
}
|
||||
|
||||
static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
|
||||
unsigned int value)
|
||||
{
|
||||
writel_relaxed(value, timer->irq_stat);
|
||||
}
|
||||
#endif /* CONFIG_ARCH_OMAP1 || CONFIG_ARCH_OMAP2PLUS */
|
||||
#endif /* __CLOCKSOURCE_DMTIMER_H */
|
||||
Reference in New Issue
Block a user