xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: meson: add regmap to the clock controllers

Browse Source 
This change registers a regmap in meson8b, gxbb and axg controllers.
The clock are still accessing their registers directly through iomem.
Once all clocks handled by these controllers have been move to regmap,
the regmap register will be removed and replaced with a syscon request.

This is needed because other drivers, such as the HDMI driver, need to
access the HHI register region

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Jerome Brunet
2018-02-12 15:58:35 +01:00
committed by Neil Armstrong
parent 1f932d9971
commit 161f6e5baa
4 changed files with 52 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/clk/meson/axg.c
View File

@@ -11,10 +11,11 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/regmap.h>
#include "clkc.h"
#include "axg.h"
@@ -791,12 +792,19 @@ static const struct of_device_id clkc_match_table[] = {
{}
};
static const struct regmap_config clkc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static int axg_clkc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct clkc_data *clkc_data;
struct resource *res;
void __iomem *clk_base;
struct regmap *map;
int ret, i;
clkc_data = of_device_get_match_data(dev);
@@ -807,12 +815,17 @@ static int axg_clkc_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -EINVAL;
clk_base = devm_ioremap(dev, res->start, resource_size(res));
if (!clk_base) {
dev_err(dev, "Unable to map clk base\n");
return -ENXIO;
}
map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config);
if (IS_ERR(map))
return PTR_ERR(map);
/* Populate base address for PLLs */
for (i = 0; i < clkc_data->clk_plls_count; i++)
clkc_data->clk_plls[i]->base = clk_base;