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clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC

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[ Upstream commit cb81719e3c1165ef1bc33137dc628f750eed8ea4 ]

The gdsc_init() function will rewrite the CLK_DIS_WAIT field while
registering the GDSC (writing the value 0x2 by default). This will
override the setting done in the driver's probe function.

Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe
function.

Fixes: 453361cdd7 ("clk: qcom: Add graphics clock controller driver for SDM845")
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230201172305.993146-2-dmitry.baryshkov@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Dmitry Baryshkov
2023-02-01 19:23:05 +02:00
committed by Greg Kroah-Hartman
parent 241048adcb
commit 15fed9258b
1 changed files with 1 additions and 6 deletions
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7
drivers/clk/qcom/gpucc-sdm845.c
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@@ -22,8 +22,6 @@
#define CX_GMU_CBCR_SLEEP_SHIFT 4 #define CX_GMU_CBCR_SLEEP_SHIFT 4
#define CX_GMU_CBCR_WAKE_MASK 0xf #define CX_GMU_CBCR_WAKE_MASK 0xf
#define CX_GMU_CBCR_WAKE_SHIFT 8 #define CX_GMU_CBCR_WAKE_SHIFT 8
#define CLK_DIS_WAIT_SHIFT 12
#define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT)
enum { enum {
P_BI_TCXO, P_BI_TCXO,
@@ -124,6 +122,7 @@ static struct clk_branch gpu_cc_cxo_clk = {
static struct gdsc gpu_cx_gdsc = { static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c, .gdscr = 0x106c,
.gds_hw_ctrl = 0x1540, .gds_hw_ctrl = 0x1540,
.clk_dis_wait_val = 0x8,
.pd = { .pd = {
.name = "gpu_cx_gdsc", .name = "gpu_cx_gdsc",
}, },
@@ -196,10 +195,6 @@ static int gpu_cc_sdm845_probe(struct platform_device *pdev)
value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value); regmap_update_bits(regmap, 0x1098, mask, value);
/* Configure clk_dis_wait for gpu_cx_gdsc */
regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
8 << CLK_DIS_WAIT_SHIFT);
return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap); return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
} }