ath10k: Fix the MTU size on QCA9377 SDIO
commit 09b8cd69edcf2be04a781e1781e98e52a775c9ad upstream.
On an imx6dl-pico-pi board with a QCA9377 SDIO chip, simply trying to
connect via ssh to another machine causes:
[ 55.824159] ath10k_sdio mmc1:0001:1: failed to transmit packet, dropping: -12
[ 55.832169] ath10k_sdio mmc1:0001:1: failed to submit frame: -12
[ 55.838529] ath10k_sdio mmc1:0001:1: failed to push frame: -12
[ 55.905863] ath10k_sdio mmc1:0001:1: failed to transmit packet, dropping: -12
[ 55.913650] ath10k_sdio mmc1:0001:1: failed to submit frame: -12
[ 55.919887] ath10k_sdio mmc1:0001:1: failed to push frame: -12
, leading to an ssh connection failure.
One user inspected the size of frames on Wireshark and reported
the followig:
"I was able to narrow the issue down to the mtu. If I set the mtu for
the wlan0 device to 1486 instead of 1500, the issue does not happen.
The size of frames that I see on Wireshark is exactly 1500 after
setting it to 1486."
Clearing the HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE avoids the problem and
the ssh command works successfully after that.
Introduce a 'credit_size_workaround' field to ath10k_hw_params for
the QCA9377 SDIO, so that the HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE
is not set in this case.
Tested with QCA9377 SDIO with firmware WLAN.TF.1.1.1-00061-QCATFSWPZ-1.
Fixes: 2f918ea986
("ath10k: enable alt data of TX path for sdio")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/20211124131047.713756-1-festevam@denx.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:

committed by
Greg Kroah-Hartman

parent
25b1a6d330
commit
15ce9329a5
@@ -89,6 +89,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = true,
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.tx_stats_over_pktlog = true,
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},
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},
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{
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{
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@@ -123,6 +124,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = true,
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.tx_stats_over_pktlog = true,
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},
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},
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{
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{
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@@ -158,6 +160,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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},
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},
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{
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{
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@@ -187,6 +190,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.num_wds_entries = 0x20,
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.uart_pin_workaround = true,
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.uart_pin_workaround = true,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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.credit_size_workaround = false,
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.bmi_large_size_download = true,
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.bmi_large_size_download = true,
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.supports_peer_stats_info = true,
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.supports_peer_stats_info = true,
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},
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},
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@@ -222,6 +226,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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},
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},
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{
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{
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@@ -256,6 +261,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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},
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},
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{
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{
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@@ -290,6 +296,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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},
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},
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{
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{
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@@ -327,6 +334,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = true,
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.fw_diag_ce_download = true,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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.supports_peer_stats_info = true,
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.supports_peer_stats_info = true,
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},
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},
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@@ -368,6 +376,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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},
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},
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{
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{
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@@ -415,6 +424,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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},
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},
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{
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{
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@@ -459,6 +469,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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},
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},
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{
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{
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@@ -493,6 +504,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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},
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},
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{
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{
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@@ -529,6 +541,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = true,
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.fw_diag_ce_download = true,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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},
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},
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{
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{
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@@ -557,6 +570,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.ast_skid_limit = 0x10,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.num_wds_entries = 0x20,
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.uart_pin_workaround = true,
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.uart_pin_workaround = true,
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.credit_size_workaround = true,
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},
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},
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{
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{
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.id = QCA4019_HW_1_0_DEV_VERSION,
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.id = QCA4019_HW_1_0_DEV_VERSION,
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@@ -597,6 +611,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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},
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},
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{
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{
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@@ -624,6 +639,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = true,
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.rri_on_ddr = true,
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.hw_filter_reset_required = false,
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.hw_filter_reset_required = false,
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.fw_diag_ce_download = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.tx_stats_over_pktlog = false,
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},
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},
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};
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};
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@@ -697,6 +713,7 @@ static void ath10k_send_suspend_complete(struct ath10k *ar)
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static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode)
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static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode)
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{
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{
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bool mtu_workaround = ar->hw_params.credit_size_workaround;
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int ret;
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int ret;
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u32 param = 0;
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u32 param = 0;
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@@ -714,7 +731,7 @@ static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode)
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param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET;
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param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET;
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if (mode == ATH10K_FIRMWARE_MODE_NORMAL)
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if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround)
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param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
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param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
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else
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else
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param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
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param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
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@@ -618,6 +618,9 @@ struct ath10k_hw_params {
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*/
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*/
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bool uart_pin_workaround;
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bool uart_pin_workaround;
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/* Workaround for the credit size calculation */
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bool credit_size_workaround;
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/* tx stats support over pktlog */
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/* tx stats support over pktlog */
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bool tx_stats_over_pktlog;
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bool tx_stats_over_pktlog;
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