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arm64/sve: Write ZCR_EL1 on context switch only if changed

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Writes to ZCR_EL1 are self-synchronising, and so may be expensive
in typical implementations.

This patch adopts the approach used for costly system register
writes elsewhere in the kernel: the system register write is
suppressed if it would not change the stored value.

Since the common case will be that of switching between tasks that
use the same vector length as one another, prediction hit rates on
the conditional branch should be reasonably good, with lower
expected amortised cost than the unconditional execution of a
heavyweight self-synchronising instruction.

Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Dave Martin
2018-05-14 18:51:09 +01:00
committed by Catalin Marinas
parent 37c3ec2d81
commit 159fd7b8d3
2 changed files with 8 additions and 6 deletions
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2
arch/arm64/kernel/entry-fpsimd.S
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@@ -49,7 +49,7 @@ ENTRY(sve_save_state)
ENDPROC(sve_save_state)
ENTRY(sve_load_state)
sve_load 0, x1, x2, 3
sve_load 0, x1, x2, 3, x4
ret
ENDPROC(sve_load_state)