drm/amdkfd: Change the control stack MTYPE from UC to NC on GFX9
CWSR fails on Raven if the control stack is MTYPE_UC, which is used for regular GART mappings. As a workaround we map it using MTYPE_NC. The MEC firmware expects the control stack at one page offset from the start of the MQD so it is part of the MQD allocation on GFXv9. AMDGPU added a memory allocation flag just for this purpose. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yong Zhao <yong.zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -457,7 +457,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
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if (kfd->kfd2kgd->init_gtt_mem_allocation(
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kfd->kgd, size, &kfd->gtt_mem,
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&kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr)){
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&kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
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false)) {
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dev_err(kfd_device, "Could not allocate %d bytes\n", size);
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goto out;
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}
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@@ -88,7 +88,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd,
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ALIGN(sizeof(struct v9_mqd), PAGE_SIZE),
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&((*mqd_mem_obj)->gtt_mem),
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&((*mqd_mem_obj)->gpu_addr),
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(void *)&((*mqd_mem_obj)->cpu_ptr));
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(void *)&((*mqd_mem_obj)->cpu_ptr), true);
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} else
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retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct v9_mqd),
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mqd_mem_obj);
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