ARC: Atomic/bitops/cmpxchg/barriers
This covers the UP / SMP (with no hardware assist for atomic r-m-w) as well as ARC700 LLOCK/SCOND insns based. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
232
arch/arc/include/asm/atomic.h
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232
arch/arc/include/asm/atomic.h
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_ARC_ATOMIC_H
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#define _ASM_ARC_ATOMIC_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/compiler.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#include <asm/smp.h>
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#define atomic_read(v) ((v)->counter)
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#ifdef CONFIG_ARC_HAS_LLSC
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#define atomic_set(v, i) (((v)->counter) = (i))
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static inline void atomic_add(int i, atomic_t *v)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" add %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp) /* Early clobber, to prevent reg reuse */
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: "r"(&v->counter), "ir"(i)
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: "cc");
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" sub %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(&v->counter), "ir"(i)
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: "cc");
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}
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/* add and also return the new value */
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" add %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(&v->counter), "ir"(i)
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: "cc");
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return temp;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" sub %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(&v->counter), "ir"(i)
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: "cc");
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return temp;
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}
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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unsigned int temp;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" bic %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(addr), "ir"(mask)
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: "cc");
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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#ifndef CONFIG_SMP
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/* violating atomic_xxx API locking protocol in UP for optimization sake */
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#define atomic_set(v, i) (((v)->counter) = (i))
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#else
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static inline void atomic_set(atomic_t *v, int i)
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{
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/*
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* Independent of hardware support, all of the atomic_xxx() APIs need
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* to follow the same locking rules to make sure that a "hardware"
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* atomic insn (e.g. LD) doesn't clobber an "emulated" atomic insn
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* sequence
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*
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* Thus atomic_set() despite being 1 insn (and seemingly atomic)
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* requires the locking.
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*/
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unsigned long flags;
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atomic_ops_lock(flags);
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v->counter = i;
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atomic_ops_unlock(flags);
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}
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#endif
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/*
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* Non hardware assisted Atomic-R-M-W
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* Locking would change to irq-disabling only (UP) and spinlocks (SMP)
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*/
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static inline void atomic_add(int i, atomic_t *v)
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{
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unsigned long flags;
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atomic_ops_lock(flags);
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v->counter += i;
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atomic_ops_unlock(flags);
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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unsigned long flags;
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atomic_ops_lock(flags);
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v->counter -= i;
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atomic_ops_unlock(flags);
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}
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long flags;
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unsigned long temp;
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atomic_ops_lock(flags);
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temp = v->counter;
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temp += i;
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v->counter = temp;
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atomic_ops_unlock(flags);
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return temp;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long flags;
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unsigned long temp;
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atomic_ops_lock(flags);
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temp = v->counter;
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temp -= i;
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v->counter = temp;
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atomic_ops_unlock(flags);
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return temp;
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}
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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unsigned long flags;
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atomic_ops_lock(flags);
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*addr &= ~mask;
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atomic_ops_unlock(flags);
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}
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#endif /* !CONFIG_ARC_HAS_LLSC */
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/**
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* __atomic_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v
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*/
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#define __atomic_add_unless(v, a, u) \
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({ \
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int c, old; \
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c = atomic_read(v); \
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while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c)\
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c = old; \
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c; \
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})
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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#define atomic_inc(v) atomic_add(1, v)
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#define atomic_dec(v) atomic_sub(1, v)
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#define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
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#define atomic_inc_return(v) atomic_add_return(1, (v))
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#define atomic_dec_return(v) atomic_sub_return(1, (v))
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#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
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#define atomic_add_negative(i, v) (atomic_add_return(i, v) < 0)
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#define ATOMIC_INIT(i) { (i) }
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#include <asm-generic/atomic64.h>
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#endif
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#endif
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#endif
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