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Merge branch 'parisc-4.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux

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Pull parisc updates from Helge Deller:
 "The most important change is that we reduce L1_CACHE_BYTES to 16
  bytes, for which a trivial patch for XPS in the network layer was
  needed.  Then we wire up the sys_membarrier and userfaultfd syscalls
  and added two other small cleanups"

* 'parisc-4.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: Change L1_CACHE_BYTES to 16
  net/xps: Fix calculation of initial number of xps queues
  parisc: reduce syslog debug output
  parisc: serial/mux: Convert to uart_console_device instead of open-coded
  parisc: Wire up userfaultfd syscall
  parisc: allocate sys_membarrier system call number
This commit is contained in:
Linus Torvalds
2015-11-04 11:30:22 -08:00
parent 1b1050cdc5 a01fece2e4
commit 14c7909290
6 changed files with 20 additions and 29 deletions
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18
arch/parisc/include/asm/cache.h
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@@ -7,20 +7,12 @@
/*
* PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
* 32-byte cachelines. The default configuration is not for SMP anyway,
* so if you're building for SMP, you should select the appropriate
* processor type. There is a potential livelock danger when running
* a machine with this value set too small, but it's more probable you'll
* just ruin performance.
* PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
* have 32-byte cachelines. The L1 length appears to be 16 bytes but this
* is not clearly documented.
*/
#ifdef CONFIG_PA20
#define L1_CACHE_BYTES 64
#define L1_CACHE_SHIFT 6
#else
#define L1_CACHE_BYTES 32
#define L1_CACHE_SHIFT 5
#endif
#define L1_CACHE_BYTES 16
#define L1_CACHE_SHIFT 4
#ifndef __ASSEMBLY__