clk: hix5hd2: add watchdog0 clocks
hix5hd2 add watchdog0 clocks Signed-off-by: Guoxiong Yan <yanguoxiong@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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@@ -60,6 +60,8 @@
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#define HIX5HD2_SD_CIU_CLK 136
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#define HIX5HD2_SD_BIU_CLK 137
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#define HIX5HD2_SD_CIU_RST 138
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#define HIX5HD2_WDG0_CLK 139
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#define HIX5HD2_WDG0_RST 140
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/* complex */
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#define HIX5HD2_MAC0_CLK 192
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