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Merge tag 'imx-dt-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

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Merge "ARM: imx: device tree updates for 3.17" from Shawn Guo:

The i.MX device tree updates for 3.17:
 - Add device tree sources and pin function header for i.MX6SX SoC
 - Initial imx6sx-sdb board support with FEC, MMC, USB, PMIC, Audio
   and GPIO key enabled
 - New board support: mbimxsd25 and mbimxsd27 from Eukrea, aristainetos
   imx6dl boards, Rex Pro and Basic, Ka-Ro TX6
 - Restructure imx6qdl-wandboard.dtsi for new rev C1 board
 - Split M28EVK and M53EVK into SoM and EVK parts
 - A few correction around SDMA, SSI and SATA device nodes
 - Add eSATA support for Cubox-i board
 - Updates on edmqmx6 to enable PCIe, I2C and CAN
 - Use DT macro for clock ID for imx27 and imx6qdl
 - Add FlexCAN support for VF610 SoC

* tag 'imx-dt-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (125 commits)
  ARM: dts: vf610: add FlexCAN node
  ARM: dts: add initial Rex Basic board support
  ARM: dts: add initial Rex Pro board support
  ARM: dts: mx5: Split M53EVK into SoM and EVK parts
  ARM: dts: imx6: RIoTboard explicitly define pad settings
  ARM: dts: vf610: fix length of eshdc1 register property
  ARM: dts: Restructure imx6qdl-wandboard.dtsi for new rev C1 board.
  ARM: dts: imx53: correct clock-names of SATA node
  ARM: imx6: Align ssi nodes between mx6 variants
  ARM: i.MX27 clk: dts: Use clock defines in DTS files
  ARM: dts: imx: correct sdma compatbile for imx6sl and imx6sx
  ARM: dts: imx6sx-sdb: Add audio support
  ARM: dts: imx6sx: Pass the fsl,fifo-depth property
  ARM: dts: imx6sx: Fix sdma node
  ARM: dts: imx6: edmqmx6: Add can bus
  ARM: dts: imx6: edmqmx6: Add two other i2c buses
  ARM: dts: imx6: edmqmx6: Add PCIe support
  ARM: dts: imx25-pdk: Add USB OTG support
  ARM: dts: i.MX53: add aipstz nodes
  ARM: dts: mxs: Split M28EVK into SoM and EVK parts
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2014-07-19 12:12:57 -07:00
parent f097748f39 69603fbbc4
commit 1409f3fd5b
189 changed files with 9494 additions and 5048 deletions
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40
include/dt-bindings/clock/imx1-clock.h Normal file
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/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX1_H
#define __DT_BINDINGS_CLOCK_IMX1_H
#define IMX1_CLK_DUMMY 0
#define IMX1_CLK_CLK32 1
#define IMX1_CLK_CLK16M_EXT 2
#define IMX1_CLK_CLK16M 3
#define IMX1_CLK_CLK32_PREMULT 4
#define IMX1_CLK_PREM 5
#define IMX1_CLK_MPLL 6
#define IMX1_CLK_MPLL_GATE 7
#define IMX1_CLK_SPLL 8
#define IMX1_CLK_SPLL_GATE 9
#define IMX1_CLK_MCU 10
#define IMX1_CLK_FCLK 11
#define IMX1_CLK_HCLK 12
#define IMX1_CLK_CLK48M 13
#define IMX1_CLK_PER1 14
#define IMX1_CLK_PER2 15
#define IMX1_CLK_PER3 16
#define IMX1_CLK_CLKO 17
#define IMX1_CLK_UART3_GATE 18
#define IMX1_CLK_SSI2_GATE 19
#define IMX1_CLK_BROM_GATE 20
#define IMX1_CLK_DMA_GATE 21
#define IMX1_CLK_CSI_GATE 22
#define IMX1_CLK_MMA_GATE 23
#define IMX1_CLK_USBD_GATE 24
#define IMX1_CLK_MAX 25
#endif

80
include/dt-bindings/clock/imx21-clock.h Normal file
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/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX21_H
#define __DT_BINDINGS_CLOCK_IMX21_H
#define IMX21_CLK_DUMMY 0
#define IMX21_CLK_CKIL 1
#define IMX21_CLK_CKIH 2
#define IMX21_CLK_FPM 3
#define IMX21_CLK_CKIH_DIV1P5 4
#define IMX21_CLK_MPLL_GATE 5
#define IMX21_CLK_SPLL_GATE 6
#define IMX21_CLK_FPM_GATE 7
#define IMX21_CLK_CKIH_GATE 8
#define IMX21_CLK_MPLL_OSC_SEL 9
#define IMX21_CLK_IPG 10
#define IMX21_CLK_HCLK 11
#define IMX21_CLK_MPLL_SEL 12
#define IMX21_CLK_SPLL_SEL 13
#define IMX21_CLK_SSI1_SEL 14
#define IMX21_CLK_SSI2_SEL 15
#define IMX21_CLK_USB_DIV 16
#define IMX21_CLK_FCLK 17
#define IMX21_CLK_MPLL 18
#define IMX21_CLK_SPLL 19
#define IMX21_CLK_NFC_DIV 20
#define IMX21_CLK_SSI1_DIV 21
#define IMX21_CLK_SSI2_DIV 22
#define IMX21_CLK_PER1 23
#define IMX21_CLK_PER2 24
#define IMX21_CLK_PER3 25
#define IMX21_CLK_PER4 26
#define IMX21_CLK_UART1_IPG_GATE 27
#define IMX21_CLK_UART2_IPG_GATE 28
#define IMX21_CLK_UART3_IPG_GATE 29
#define IMX21_CLK_UART4_IPG_GATE 30
#define IMX21_CLK_CSPI1_IPG_GATE 31
#define IMX21_CLK_CSPI2_IPG_GATE 32
#define IMX21_CLK_SSI1_GATE 33
#define IMX21_CLK_SSI2_GATE 34
#define IMX21_CLK_SDHC1_IPG_GATE 35
#define IMX21_CLK_SDHC2_IPG_GATE 36
#define IMX21_CLK_GPIO_GATE 37
#define IMX21_CLK_I2C_GATE 38
#define IMX21_CLK_DMA_GATE 39
#define IMX21_CLK_USB_GATE 40
#define IMX21_CLK_EMMA_GATE 41
#define IMX21_CLK_SSI2_BAUD_GATE 42
#define IMX21_CLK_SSI1_BAUD_GATE 43
#define IMX21_CLK_LCDC_IPG_GATE 44
#define IMX21_CLK_NFC_GATE 45
#define IMX21_CLK_LCDC_HCLK_GATE 46
#define IMX21_CLK_PER4_GATE 47
#define IMX21_CLK_BMI_GATE 48
#define IMX21_CLK_USB_HCLK_GATE 49
#define IMX21_CLK_SLCDC_GATE 50
#define IMX21_CLK_SLCDC_HCLK_GATE 51
#define IMX21_CLK_EMMA_HCLK_GATE 52
#define IMX21_CLK_BROM_GATE 53
#define IMX21_CLK_DMA_HCLK_GATE 54
#define IMX21_CLK_CSI_HCLK_GATE 55
#define IMX21_CLK_CSPI3_IPG_GATE 56
#define IMX21_CLK_WDOG_GATE 57
#define IMX21_CLK_GPT1_IPG_GATE 58
#define IMX21_CLK_GPT2_IPG_GATE 59
#define IMX21_CLK_GPT3_IPG_GATE 60
#define IMX21_CLK_PWM_IPG_GATE 61
#define IMX21_CLK_RTC_GATE 62
#define IMX21_CLK_KPP_GATE 63
#define IMX21_CLK_OWIRE_GATE 64
#define IMX21_CLK_MAX 65
#endif

108
include/dt-bindings/clock/imx27-clock.h Normal file
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/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX27_H
#define __DT_BINDINGS_CLOCK_IMX27_H
#define IMX27_CLK_DUMMY 0
#define IMX27_CLK_CKIH 1
#define IMX27_CLK_CKIL 2
#define IMX27_CLK_MPLL 3
#define IMX27_CLK_SPLL 4
#define IMX27_CLK_MPLL_MAIN2 5
#define IMX27_CLK_AHB 6
#define IMX27_CLK_IPG 7
#define IMX27_CLK_NFC_DIV 8
#define IMX27_CLK_PER1_DIV 9
#define IMX27_CLK_PER2_DIV 10
#define IMX27_CLK_PER3_DIV 11
#define IMX27_CLK_PER4_DIV 12
#define IMX27_CLK_VPU_SEL 13
#define IMX27_CLK_VPU_DIV 14
#define IMX27_CLK_USB_DIV 15
#define IMX27_CLK_CPU_SEL 16
#define IMX27_CLK_CLKO_SEL 17
#define IMX27_CLK_CPU_DIV 18
#define IMX27_CLK_CLKO_DIV 19
#define IMX27_CLK_SSI1_SEL 20
#define IMX27_CLK_SSI2_SEL 21
#define IMX27_CLK_SSI1_DIV 22
#define IMX27_CLK_SSI2_DIV 23
#define IMX27_CLK_CLKO_EN 24
#define IMX27_CLK_SSI2_IPG_GATE 25
#define IMX27_CLK_SSI1_IPG_GATE 26
#define IMX27_CLK_SLCDC_IPG_GATE 27
#define IMX27_CLK_SDHC3_IPG_GATE 28
#define IMX27_CLK_SDHC2_IPG_GATE 29
#define IMX27_CLK_SDHC1_IPG_GATE 30
#define IMX27_CLK_SCC_IPG_GATE 31
#define IMX27_CLK_SAHARA_IPG_GATE 32
#define IMX27_CLK_RTC_IPG_GATE 33
#define IMX27_CLK_PWM_IPG_GATE 34
#define IMX27_CLK_OWIRE_IPG_GATE 35
#define IMX27_CLK_LCDC_IPG_GATE 36
#define IMX27_CLK_KPP_IPG_GATE 37
#define IMX27_CLK_IIM_IPG_GATE 38
#define IMX27_CLK_I2C2_IPG_GATE 39
#define IMX27_CLK_I2C1_IPG_GATE 40
#define IMX27_CLK_GPT6_IPG_GATE 41
#define IMX27_CLK_GPT5_IPG_GATE 42
#define IMX27_CLK_GPT4_IPG_GATE 43
#define IMX27_CLK_GPT3_IPG_GATE 44
#define IMX27_CLK_GPT2_IPG_GATE 45
#define IMX27_CLK_GPT1_IPG_GATE 46
#define IMX27_CLK_GPIO_IPG_GATE 47
#define IMX27_CLK_FEC_IPG_GATE 48
#define IMX27_CLK_EMMA_IPG_GATE 49
#define IMX27_CLK_DMA_IPG_GATE 50
#define IMX27_CLK_CSPI3_IPG_GATE 51
#define IMX27_CLK_CSPI2_IPG_GATE 52
#define IMX27_CLK_CSPI1_IPG_GATE 53
#define IMX27_CLK_NFC_BAUD_GATE 54
#define IMX27_CLK_SSI2_BAUD_GATE 55
#define IMX27_CLK_SSI1_BAUD_GATE 56
#define IMX27_CLK_VPU_BAUD_GATE 57
#define IMX27_CLK_PER4_GATE 58
#define IMX27_CLK_PER3_GATE 59
#define IMX27_CLK_PER2_GATE 60
#define IMX27_CLK_PER1_GATE 61
#define IMX27_CLK_USB_AHB_GATE 62
#define IMX27_CLK_SLCDC_AHB_GATE 63
#define IMX27_CLK_SAHARA_AHB_GATE 64
#define IMX27_CLK_LCDC_AHB_GATE 65
#define IMX27_CLK_VPU_AHB_GATE 66
#define IMX27_CLK_FEC_AHB_GATE 67
#define IMX27_CLK_EMMA_AHB_GATE 68
#define IMX27_CLK_EMI_AHB_GATE 69
#define IMX27_CLK_DMA_AHB_GATE 70
#define IMX27_CLK_CSI_AHB_GATE 71
#define IMX27_CLK_BROM_AHB_GATE 72
#define IMX27_CLK_ATA_AHB_GATE 73
#define IMX27_CLK_WDOG_IPG_GATE 74
#define IMX27_CLK_USB_IPG_GATE 75
#define IMX27_CLK_UART6_IPG_GATE 76
#define IMX27_CLK_UART5_IPG_GATE 77
#define IMX27_CLK_UART4_IPG_GATE 78
#define IMX27_CLK_UART3_IPG_GATE 79
#define IMX27_CLK_UART2_IPG_GATE 80
#define IMX27_CLK_UART1_IPG_GATE 81
#define IMX27_CLK_CKIH_DIV1P5 82
#define IMX27_CLK_FPM 83
#define IMX27_CLK_MPLL_OSC_SEL 84
#define IMX27_CLK_MPLL_SEL 85
#define IMX27_CLK_SPLL_GATE 86
#define IMX27_CLK_MSHC_DIV 87
#define IMX27_CLK_RTIC_IPG_GATE 88
#define IMX27_CLK_MSHC_IPG_GATE 89
#define IMX27_CLK_RTIC_AHB_GATE 90
#define IMX27_CLK_MSHC_BAUD_GATE 91
#define IMX27_CLK_CKIH_GATE 92
#define IMX27_CLK_MAX 93
#endif

224
include/dt-bindings/clock/imx6qdl-clock.h Normal file
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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
#define __DT_BINDINGS_CLOCK_IMX6QDL_H
#define IMX6QDL_CLK_DUMMY 0
#define IMX6QDL_CLK_CKIL 1
#define IMX6QDL_CLK_CKIH 2
#define IMX6QDL_CLK_OSC 3
#define IMX6QDL_CLK_PLL2_PFD0_352M 4
#define IMX6QDL_CLK_PLL2_PFD1_594M 5
#define IMX6QDL_CLK_PLL2_PFD2_396M 6
#define IMX6QDL_CLK_PLL3_PFD0_720M 7
#define IMX6QDL_CLK_PLL3_PFD1_540M 8
#define IMX6QDL_CLK_PLL3_PFD2_508M 9
#define IMX6QDL_CLK_PLL3_PFD3_454M 10
#define IMX6QDL_CLK_PLL2_198M 11
#define IMX6QDL_CLK_PLL3_120M 12
#define IMX6QDL_CLK_PLL3_80M 13
#define IMX6QDL_CLK_PLL3_60M 14
#define IMX6QDL_CLK_TWD 15
#define IMX6QDL_CLK_STEP 16
#define IMX6QDL_CLK_PLL1_SW 17
#define IMX6QDL_CLK_PERIPH_PRE 18
#define IMX6QDL_CLK_PERIPH2_PRE 19
#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
#define IMX6QDL_CLK_AXI_SEL 22
#define IMX6QDL_CLK_ESAI_SEL 23
#define IMX6QDL_CLK_ASRC_SEL 24
#define IMX6QDL_CLK_SPDIF_SEL 25
#define IMX6QDL_CLK_GPU2D_AXI 26
#define IMX6QDL_CLK_GPU3D_AXI 27
#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
#define IMX6QDL_CLK_IPU1_SEL 31
#define IMX6QDL_CLK_IPU2_SEL 32
#define IMX6QDL_CLK_LDB_DI0_SEL 33
#define IMX6QDL_CLK_LDB_DI1_SEL 34
#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
#define IMX6QDL_CLK_IPU1_DI0_SEL 39
#define IMX6QDL_CLK_IPU1_DI1_SEL 40
#define IMX6QDL_CLK_IPU2_DI0_SEL 41
#define IMX6QDL_CLK_IPU2_DI1_SEL 42
#define IMX6QDL_CLK_HSI_TX_SEL 43
#define IMX6QDL_CLK_PCIE_AXI_SEL 44
#define IMX6QDL_CLK_SSI1_SEL 45
#define IMX6QDL_CLK_SSI2_SEL 46
#define IMX6QDL_CLK_SSI3_SEL 47
#define IMX6QDL_CLK_USDHC1_SEL 48
#define IMX6QDL_CLK_USDHC2_SEL 49
#define IMX6QDL_CLK_USDHC3_SEL 50
#define IMX6QDL_CLK_USDHC4_SEL 51
#define IMX6QDL_CLK_ENFC_SEL 52
#define IMX6QDL_CLK_EMI_SEL 53
#define IMX6QDL_CLK_EMI_SLOW_SEL 54
#define IMX6QDL_CLK_VDO_AXI_SEL 55
#define IMX6QDL_CLK_VPU_AXI_SEL 56
#define IMX6QDL_CLK_CKO1_SEL 57
#define IMX6QDL_CLK_PERIPH 58
#define IMX6QDL_CLK_PERIPH2 59
#define IMX6QDL_CLK_PERIPH_CLK2 60
#define IMX6QDL_CLK_PERIPH2_CLK2 61
#define IMX6QDL_CLK_IPG 62
#define IMX6QDL_CLK_IPG_PER 63
#define IMX6QDL_CLK_ESAI_PRED 64
#define IMX6QDL_CLK_ESAI_PODF 65
#define IMX6QDL_CLK_ASRC_PRED 66
#define IMX6QDL_CLK_ASRC_PODF 67
#define IMX6QDL_CLK_SPDIF_PRED 68
#define IMX6QDL_CLK_SPDIF_PODF 69
#define IMX6QDL_CLK_CAN_ROOT 70
#define IMX6QDL_CLK_ECSPI_ROOT 71
#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
#define IMX6QDL_CLK_GPU3D_SHADER 74
#define IMX6QDL_CLK_IPU1_PODF 75
#define IMX6QDL_CLK_IPU2_PODF 76
#define IMX6QDL_CLK_LDB_DI0_PODF 77
#define IMX6QDL_CLK_LDB_DI1_PODF 78
#define IMX6QDL_CLK_IPU1_DI0_PRE 79
#define IMX6QDL_CLK_IPU1_DI1_PRE 80
#define IMX6QDL_CLK_IPU2_DI0_PRE 81
#define IMX6QDL_CLK_IPU2_DI1_PRE 82
#define IMX6QDL_CLK_HSI_TX_PODF 83
#define IMX6QDL_CLK_SSI1_PRED 84
#define IMX6QDL_CLK_SSI1_PODF 85
#define IMX6QDL_CLK_SSI2_PRED 86
#define IMX6QDL_CLK_SSI2_PODF 87
#define IMX6QDL_CLK_SSI3_PRED 88
#define IMX6QDL_CLK_SSI3_PODF 89
#define IMX6QDL_CLK_UART_SERIAL_PODF 90
#define IMX6QDL_CLK_USDHC1_PODF 91
#define IMX6QDL_CLK_USDHC2_PODF 92
#define IMX6QDL_CLK_USDHC3_PODF 93
#define IMX6QDL_CLK_USDHC4_PODF 94
#define IMX6QDL_CLK_ENFC_PRED 95
#define IMX6QDL_CLK_ENFC_PODF 96
#define IMX6QDL_CLK_EMI_PODF 97
#define IMX6QDL_CLK_EMI_SLOW_PODF 98
#define IMX6QDL_CLK_VPU_AXI_PODF 99
#define IMX6QDL_CLK_CKO1_PODF 100
#define IMX6QDL_CLK_AXI 101
#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
#define IMX6QDL_CLK_ARM 104
#define IMX6QDL_CLK_AHB 105
#define IMX6QDL_CLK_APBH_DMA 106
#define IMX6QDL_CLK_ASRC 107
#define IMX6QDL_CLK_CAN1_IPG 108
#define IMX6QDL_CLK_CAN1_SERIAL 109
#define IMX6QDL_CLK_CAN2_IPG 110
#define IMX6QDL_CLK_CAN2_SERIAL 111
#define IMX6QDL_CLK_ECSPI1 112
#define IMX6QDL_CLK_ECSPI2 113
#define IMX6QDL_CLK_ECSPI3 114
#define IMX6QDL_CLK_ECSPI4 115
#define IMX6Q_CLK_ECSPI5 116
#define IMX6DL_CLK_I2C4 116
#define IMX6QDL_CLK_ENET 117
#define IMX6QDL_CLK_ESAI 118
#define IMX6QDL_CLK_GPT_IPG 119
#define IMX6QDL_CLK_GPT_IPG_PER 120
#define IMX6QDL_CLK_GPU2D_CORE 121
#define IMX6QDL_CLK_GPU3D_CORE 122
#define IMX6QDL_CLK_HDMI_IAHB 123
#define IMX6QDL_CLK_HDMI_ISFR 124
#define IMX6QDL_CLK_I2C1 125
#define IMX6QDL_CLK_I2C2 126
#define IMX6QDL_CLK_I2C3 127
#define IMX6QDL_CLK_IIM 128
#define IMX6QDL_CLK_ENFC 129
#define IMX6QDL_CLK_IPU1 130
#define IMX6QDL_CLK_IPU1_DI0 131
#define IMX6QDL_CLK_IPU1_DI1 132
#define IMX6QDL_CLK_IPU2 133
#define IMX6QDL_CLK_IPU2_DI0 134
#define IMX6QDL_CLK_LDB_DI0 135
#define IMX6QDL_CLK_LDB_DI1 136
#define IMX6QDL_CLK_IPU2_DI1 137
#define IMX6QDL_CLK_HSI_TX 138
#define IMX6QDL_CLK_MLB 139
#define IMX6QDL_CLK_MMDC_CH0_AXI 140
#define IMX6QDL_CLK_MMDC_CH1_AXI 141
#define IMX6QDL_CLK_OCRAM 142
#define IMX6QDL_CLK_OPENVG_AXI 143
#define IMX6QDL_CLK_PCIE_AXI 144
#define IMX6QDL_CLK_PWM1 145
#define IMX6QDL_CLK_PWM2 146
#define IMX6QDL_CLK_PWM3 147
#define IMX6QDL_CLK_PWM4 148
#define IMX6QDL_CLK_PER1_BCH 149
#define IMX6QDL_CLK_GPMI_BCH_APB 150
#define IMX6QDL_CLK_GPMI_BCH 151
#define IMX6QDL_CLK_GPMI_IO 152
#define IMX6QDL_CLK_GPMI_APB 153
#define IMX6QDL_CLK_SATA 154
#define IMX6QDL_CLK_SDMA 155
#define IMX6QDL_CLK_SPBA 156
#define IMX6QDL_CLK_SSI1 157
#define IMX6QDL_CLK_SSI2 158
#define IMX6QDL_CLK_SSI3 159
#define IMX6QDL_CLK_UART_IPG 160
#define IMX6QDL_CLK_UART_SERIAL 161
#define IMX6QDL_CLK_USBOH3 162
#define IMX6QDL_CLK_USDHC1 163
#define IMX6QDL_CLK_USDHC2 164
#define IMX6QDL_CLK_USDHC3 165
#define IMX6QDL_CLK_USDHC4 166
#define IMX6QDL_CLK_VDO_AXI 167
#define IMX6QDL_CLK_VPU_AXI 168
#define IMX6QDL_CLK_CKO1 169
#define IMX6QDL_CLK_PLL1_SYS 170
#define IMX6QDL_CLK_PLL2_BUS 171
#define IMX6QDL_CLK_PLL3_USB_OTG 172
#define IMX6QDL_CLK_PLL4_AUDIO 173
#define IMX6QDL_CLK_PLL5_VIDEO 174
#define IMX6QDL_CLK_PLL8_MLB 175
#define IMX6QDL_CLK_PLL7_USB_HOST 176
#define IMX6QDL_CLK_PLL6_ENET 177
#define IMX6QDL_CLK_SSI1_IPG 178
#define IMX6QDL_CLK_SSI2_IPG 179
#define IMX6QDL_CLK_SSI3_IPG 180
#define IMX6QDL_CLK_ROM 181
#define IMX6QDL_CLK_USBPHY1 182
#define IMX6QDL_CLK_USBPHY2 183
#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
#define IMX6QDL_CLK_SATA_REF 186
#define IMX6QDL_CLK_SATA_REF_100M 187
#define IMX6QDL_CLK_PCIE_REF 188
#define IMX6QDL_CLK_PCIE_REF_125M 189
#define IMX6QDL_CLK_ENET_REF 190
#define IMX6QDL_CLK_USBPHY1_GATE 191
#define IMX6QDL_CLK_USBPHY2_GATE 192
#define IMX6QDL_CLK_PLL4_POST_DIV 193
#define IMX6QDL_CLK_PLL5_POST_DIV 194
#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
#define IMX6QDL_CLK_EIM_SLOW 196
#define IMX6QDL_CLK_SPDIF 197
#define IMX6QDL_CLK_CKO2_SEL 198
#define IMX6QDL_CLK_CKO2_PODF 199
#define IMX6QDL_CLK_CKO2 200
#define IMX6QDL_CLK_CKO 201
#define IMX6QDL_CLK_VDOA 202
#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
#define IMX6QDL_CLK_LVDS1_SEL 204
#define IMX6QDL_CLK_LVDS2_SEL 205
#define IMX6QDL_CLK_LVDS1_GATE 206
#define IMX6QDL_CLK_LVDS2_GATE 207
#define IMX6QDL_CLK_ESAI_AHB 208
#define IMX6QDL_CLK_END 209
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */

4
include/dt-bindings/clock/vf610-clock.h
View File

@@ -164,6 +164,8 @@
#define VF610_CLK_DMAMUX1 151
#define VF610_CLK_DMAMUX2 152
#define VF610_CLK_DMAMUX3 153
#define VF610_CLK_END 154
#define VF610_CLK_FLEXCAN0_EN 154
#define VF610_CLK_FLEXCAN1_EN 155
#define VF610_CLK_END 156
#endif /* __DT_BINDINGS_CLOCK_VF610_H */