Merge branch 'x86-timers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 timer updates from Thomas Gleixner: "Early TSC based time stamping to allow better boot time analysis. This comes with a general cleanup of the TSC calibration code which grew warts and duct taping over the years and removes 250 lines of code. Initiated and mostly implemented by Pavel with help from various folks" * 'x86-timers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (37 commits) x86/kvmclock: Mark kvm_get_preset_lpj() as __init x86/tsc: Consolidate init code sched/clock: Disable interrupts when calling generic_sched_clock_init() timekeeping: Prevent false warning when persistent clock is not available sched/clock: Close a hole in sched_clock_init() x86/tsc: Make use of tsc_calibrate_cpu_early() x86/tsc: Split native_calibrate_cpu() into early and late parts sched/clock: Use static key for sched_clock_running sched/clock: Enable sched clock early sched/clock: Move sched clock initialization and merge with generic clock x86/tsc: Use TSC as sched clock early x86/tsc: Initialize cyc2ns when tsc frequency is determined x86/tsc: Calibrate tsc only once ARM/time: Remove read_boot_clock64() s390/time: Remove read_boot_clock64() timekeeping: Default boot time offset to local_clock() timekeeping: Replace read_boot_clock64() with read_persistent_wall_and_boot_offset() s390/time: Add read_persistent_wall_and_boot_offset() x86/xen/time: Output xen sched_clock time from 0 x86/xen/time: Initialize pv xen time in init_hypervisor_platform() ...
这个提交包含在：
Linus Torvalds
@@ -1,4 +1,4 @@
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obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o mrfld.o pwr.o
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obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o pwr.o
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# SFI specific code
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ifdef CONFIG_X86_INTEL_MID
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@@ -36,8 +36,6 @@
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#include <asm/apb_timer.h>
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#include <asm/reboot.h>
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#include "intel_mid_weak_decls.h"
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/*
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* the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
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* cmdline option x86_intel_mid_timer can be used to override the configuration
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@@ -61,10 +59,6 @@
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enum intel_mid_timer_options intel_mid_timer_options;
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/* intel_mid_ops to store sub arch ops */
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static struct intel_mid_ops *intel_mid_ops;
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/* getter function for sub arch ops*/
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static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;
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enum intel_mid_cpu_type __intel_mid_cpu_chip;
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EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
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@@ -82,11 +76,6 @@ static void intel_mid_reboot(void)
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intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
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}
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static unsigned long __init intel_mid_calibrate_tsc(void)
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{
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return 0;
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}
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static void __init intel_mid_setup_bp_timer(void)
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{
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apbt_time_init();
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@@ -133,6 +122,7 @@ static void intel_mid_arch_setup(void)
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case 0x3C:
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case 0x4A:
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__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
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x86_platform.legacy.rtc = 1;
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break;
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case 0x27:
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default:
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@@ -140,17 +130,7 @@ static void intel_mid_arch_setup(void)
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break;
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}
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if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops))
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intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
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else {
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intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
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pr_info("ARCH: Unknown SoC, assuming Penwell!\n");
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}
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out:
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if (intel_mid_ops->arch_setup)
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intel_mid_ops->arch_setup();
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/*
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* Intel MID platforms are using explicitly defined regulators.
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*
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@@ -191,7 +171,6 @@ void __init x86_intel_mid_early_setup(void)
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x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
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x86_platform.calibrate_tsc = intel_mid_calibrate_tsc;
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x86_platform.get_nmi_reason = intel_mid_get_nmi_reason;
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x86_init.pci.arch_init = intel_mid_pci_init;
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@@ -1,18 +0,0 @@
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/*
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* intel_mid_weak_decls.h: Weak declarations of intel-mid.c
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*
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* (C) Copyright 2013 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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/* For every CPU addition a new get_<cpuname>_ops interface needs
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* to be added.
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*/
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extern void *get_penwell_ops(void);
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extern void *get_cloverview_ops(void);
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extern void *get_tangier_ops(void);
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@@ -1,70 +0,0 @@
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/*
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* mfld.c: Intel Medfield platform setup code
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*
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* (C) Copyright 2013 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/init.h>
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#include <asm/apic.h>
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#include <asm/intel-mid.h>
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#include <asm/intel_mid_vrtc.h>
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#include "intel_mid_weak_decls.h"
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static unsigned long __init mfld_calibrate_tsc(void)
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{
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unsigned long fast_calibrate;
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u32 lo, hi, ratio, fsb;
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
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ratio = (hi >> 8) & 0x1f;
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pr_debug("ratio is %d\n", ratio);
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if (!ratio) {
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pr_err("read a zero ratio, should be incorrect!\n");
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pr_err("force tsc ratio to 16 ...\n");
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ratio = 16;
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}
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rdmsr(MSR_FSB_FREQ, lo, hi);
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if ((lo & 0x7) == 0x7)
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fsb = FSB_FREQ_83SKU;
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else
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fsb = FSB_FREQ_100SKU;
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fast_calibrate = ratio * fsb;
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pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
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lapic_timer_frequency = fsb * 1000 / HZ;
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/*
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* TSC on Intel Atom SoCs is reliable and of known frequency.
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* See tsc_msr.c for details.
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*/
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setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
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setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
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return fast_calibrate;
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}
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static void __init penwell_arch_setup(void)
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{
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x86_platform.calibrate_tsc = mfld_calibrate_tsc;
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}
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static struct intel_mid_ops penwell_ops = {
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.arch_setup = penwell_arch_setup,
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};
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void *get_penwell_ops(void)
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{
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return &penwell_ops;
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}
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void *get_cloverview_ops(void)
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{
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return &penwell_ops;
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}
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@@ -1,105 +0,0 @@
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/*
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* Intel Merrifield platform specific setup code
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*
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* (C) Copyright 2013 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/init.h>
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#include <asm/apic.h>
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#include <asm/intel-mid.h>
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#include "intel_mid_weak_decls.h"
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static unsigned long __init tangier_calibrate_tsc(void)
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{
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unsigned long fast_calibrate;
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u32 lo, hi, ratio, fsb, bus_freq;
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/* *********************** */
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/* Compute TSC:Ratio * FSB */
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/* *********************** */
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/* Compute Ratio */
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rdmsr(MSR_PLATFORM_INFO, lo, hi);
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pr_debug("IA32 PLATFORM_INFO is 0x%x : %x\n", hi, lo);
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ratio = (lo >> 8) & 0xFF;
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pr_debug("ratio is %d\n", ratio);
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if (!ratio) {
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pr_err("Read a zero ratio, force tsc ratio to 4 ...\n");
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ratio = 4;
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}
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/* Compute FSB */
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rdmsr(MSR_FSB_FREQ, lo, hi);
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pr_debug("Actual FSB frequency detected by SOC 0x%x : %x\n",
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hi, lo);
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bus_freq = lo & 0x7;
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pr_debug("bus_freq = 0x%x\n", bus_freq);
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if (bus_freq == 0)
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fsb = FSB_FREQ_100SKU;
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else if (bus_freq == 1)
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fsb = FSB_FREQ_100SKU;
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else if (bus_freq == 2)
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fsb = FSB_FREQ_133SKU;
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else if (bus_freq == 3)
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fsb = FSB_FREQ_167SKU;
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else if (bus_freq == 4)
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fsb = FSB_FREQ_83SKU;
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else if (bus_freq == 5)
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fsb = FSB_FREQ_400SKU;
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else if (bus_freq == 6)
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fsb = FSB_FREQ_267SKU;
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else if (bus_freq == 7)
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fsb = FSB_FREQ_333SKU;
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else {
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BUG();
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pr_err("Invalid bus_freq! Setting to minimal value!\n");
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fsb = FSB_FREQ_100SKU;
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}
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/* TSC = FSB Freq * Resolved HFM Ratio */
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fast_calibrate = ratio * fsb;
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pr_debug("calculate tangier tsc %lu KHz\n", fast_calibrate);
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/* ************************************ */
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/* Calculate Local APIC Timer Frequency */
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/* ************************************ */
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lapic_timer_frequency = (fsb * 1000) / HZ;
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pr_debug("Setting lapic_timer_frequency = %d\n",
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lapic_timer_frequency);
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/*
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* TSC on Intel Atom SoCs is reliable and of known frequency.
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* See tsc_msr.c for details.
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*/
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setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
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setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
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return fast_calibrate;
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}
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static void __init tangier_arch_setup(void)
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{
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x86_platform.calibrate_tsc = tangier_calibrate_tsc;
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x86_platform.legacy.rtc = 1;
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}
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/* tangier arch ops */
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static struct intel_mid_ops tangier_ops = {
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.arch_setup = tangier_arch_setup,
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};
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void *get_tangier_ops(void)
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{
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return &tangier_ops;
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}
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