Merge tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie: "This starts to support NVIDIA volta hardware with nouveau, and adds amdgpu support for the GPU in the Kabylake-G (the intel + radeon single package chip), along with some initial Intel icelake enabling. Summary: New Drivers: - v3d - driver for broadcom V3D V3.x+ hardware - xen-front - XEN PV display frontend core: - handle zpos normalization in the core - stop looking at legacy pointers in atomic paths - improved scheduler documentation - improved aspect ratio validation - aspect ratio support for 64:27 and 256:135 - drop unused control node code. i915: - Icelake (ICL) enabling - GuC/HuC refactoring - PSR/PSR2 enabling and fixes - DPLL management refactoring - DP MST fixes - NV12 enabling - HDCP improvements - GEM/Execlist/reset improvements - GVT improvements - stolen memory first 4k fix amdgpu: - Vega 20 support - VEGAM support (Kabylake-G) - preOS scanout buffer reservation - power management gfxoff support for raven - SR-IOV fixes - Vega10 power profiles and clock voltage control - scatter/gather display support on CZ/ST amdkfd: - GFX9 dGPU support - userptr memory mapping nouveau: - major refactoring for Volta GV100 support tda998x: - HDMI i2c CEC support etnaviv: - removed unused logging code - license text cleanups - MMU handling improvements - timeout fence fix for 50 days uptime tegra: - IOMMU support in gr2d/gr3d drivers - zpos support vc4: - syncobj support - CTM, plane alpha and async cursor support analogix_dp: - HPD and aux chan fixes sun4i: - MIPI DSI support tilcdc: - clock divider fixes for OMAP-l138 LCDK board rcar-du: - R8A77965 support - dma-buf fences fixes - hardware indexed crtc/du group handling - generic zplane property support atmel-hclcdc: - generic zplane property support mediatek: - use generic video mode function exynos: - S5PV210 FIMD variant support - IPP v2 framework - more HW overlays support" * tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm: (1286 commits) drm/amdgpu: fix 32-bit build warning drm/exynos: fimc: signedness bug in fimc_setup_clocks() drm/exynos: scaler: fix static checker warning drm/amdgpu: Use dev_info() to report amdkfd is not supported for this ASIC drm/amd/display: Remove use of division operator for long longs drm/amdgpu: Update GFX info structure to match what vega20 used drm/amdgpu/pp: remove duplicate assignment drm/sched: add rcu_barrier after entity fini drm/amdgpu: move VM BOs on LRU again drm/amdgpu: consistenly use VM moved flag drm/amdgpu: kmap PDs/PTs in amdgpu_vm_update_directories drm/amdgpu: further optimize amdgpu_vm_handle_moved drm/amdgpu: cleanup amdgpu_vm_validate_pt_bos v2 drm/amdgpu: rework VM state machine lock handling v2 drm/amdgpu: Add runtime VCN PG support drm/amdgpu: Enable VCN static PG by default on RV drm/amdgpu: Add VCN static PG support on RV drm/amdgpu: Enable VCN CG by default on RV drm/amdgpu: Add static CG control for VCN on RV drm/exynos: Fix default value for zpos plane property ...
Este commit está contenido en:
Linus Torvalds
@@ -14,7 +14,13 @@ Required properties:
|
||||
"adi,adv7513"
|
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"adi,adv7533"
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|
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- reg: I2C slave address
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- reg: I2C slave addresses
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The ADV7511 internal registers are split into four pages exposed through
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different I2C addresses, creating four register maps. Each map has it own
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I2C address and acts as a standard slave device on the I2C bus. The main
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address is mandatory, others are optional and revert to defaults if not
|
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specified.
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|
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The ADV7511 supports a large number of input data formats that differ by their
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color depth, color format, clock mode, bit justification and random
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@@ -70,6 +76,9 @@ Optional properties:
|
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rather than generate its own timings for HDMI output.
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- clocks: from common clock binding: reference to the CEC clock.
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- clock-names: from common clock binding: must be "cec".
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- reg-names : Names of maps with programmable addresses.
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It can contain any map needing a non-default address.
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Possible maps names are : "main", "edid", "cec", "packet"
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Required nodes:
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@@ -88,7 +97,12 @@ Example
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adv7511w: hdmi@39 {
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compatible = "adi,adv7511w";
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reg = <39>;
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/*
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* The EDID page will be accessible on address 0x66 on the I2C
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* bus. All other maps continue to use their default addresses.
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*/
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reg = <0x39>, <0x66>;
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reg-names = "main", "edid";
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interrupt-parent = <&gpio3>;
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interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
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clocks = <&cec_clock>;
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133
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
Archivo normal
133
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
Archivo normal
@@ -0,0 +1,133 @@
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Cadence DSI bridge
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==================
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The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
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Required properties:
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- compatible: should be set to "cdns,dsi".
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- reg: physical base address and length of the controller's registers.
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- interrupts: interrupt line connected to the DSI bridge.
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- clocks: DSI bridge clocks.
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- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
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- phys: phandle link to the MIPI D-PHY controller.
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- phy-names: must contain "dphy".
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- #address-cells: must be set to 1.
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- #size-cells: must be set to 0.
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Optional properties:
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- resets: DSI reset lines.
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- reset-names: can contain "dsi_p_rst".
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Required subnodes:
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- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
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2 ports are available:
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* port 0: this port is only needed if some of your DSI devices are
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controlled through an external bus like I2C or SPI. Can have at
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most 4 endpoints. The endpoint number is directly encoding the
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DSI virtual channel used by this device.
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* port 1: represents the DPI input.
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Other ports will be added later to support the new kind of inputs.
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- one subnode per DSI device connected on the DSI bus. Each DSI device should
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contain a reg property encoding its virtual channel.
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Cadence DPHY
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============
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Cadence DPHY block.
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Required properties:
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- compatible: should be set to "cdns,dphy".
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- reg: physical base address and length of the DPHY registers.
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- clocks: DPHY reference clocks.
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- clock-names: must contain "psm" and "pll_ref".
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- #phy-cells: must be set to 0.
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Example:
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dphy0: dphy@fd0e0000{
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compatible = "cdns,dphy";
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reg = <0x0 0xfd0e0000 0x0 0x1000>;
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clocks = <&psm_clk>, <&pll_ref_clk>;
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clock-names = "psm", "pll_ref";
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#phy-cells = <0>;
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};
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dsi0: dsi@fd0c0000 {
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compatible = "cdns,dsi";
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reg = <0x0 0xfd0c0000 0x0 0x1000>;
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clocks = <&pclk>, <&sysclk>;
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clock-names = "dsi_p_clk", "dsi_sys_clk";
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interrupts = <1>;
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phys = <&dphy0>;
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phy-names = "dphy";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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dsi0_dpi_input: endpoint {
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remote-endpoint = <&xxx_dpi_output>;
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};
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};
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};
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panel: dsi-dev@0 {
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compatible = "<vendor,panel>";
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reg = <0>;
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};
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};
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or
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dsi0: dsi@fd0c0000 {
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compatible = "cdns,dsi";
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reg = <0x0 0xfd0c0000 0x0 0x1000>;
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clocks = <&pclk>, <&sysclk>;
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clock-names = "dsi_p_clk", "dsi_sys_clk";
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interrupts = <1>;
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phys = <&dphy1>;
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phy-names = "dphy";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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dsi0_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dsi_panel_input>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_dpi_input: endpoint {
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remote-endpoint = <&xxx_dpi_output>;
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};
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};
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};
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};
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i2c@xxx {
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panel: panel@59 {
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compatible = "<vendor,panel>";
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reg = <0x59>;
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port {
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dsi_panel_input: endpoint {
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remote-endpoint = <&dsi0_output>;
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};
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};
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};
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};
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@@ -14,6 +14,7 @@ Required properties:
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- compatible : Shall contain one or more of
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- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
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- "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
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- "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
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- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
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When compatible with generic versions, nodes must list the SoC-specific
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@@ -27,6 +27,9 @@ Optional properties:
|
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in question is used. The implementation allows one or two DAIs. If two
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DAIs are defined, they must be of different type.
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- nxp,calib-gpios: calibration GPIO, which must correspond with the
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gpio used for the TDA998x interrupt pin.
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[1] Documentation/sound/alsa/soc/DAI.txt
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[2] include/dt-bindings/display/tda998x.h
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|
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|
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60
Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt
Archivo normal
60
Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt
Archivo normal
@@ -0,0 +1,60 @@
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Thine Electronics THC63LVD1024 LVDS decoder
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-------------------------------------------
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|
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The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS streams
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to parallel data outputs. The chip supports single/dual input/output modes,
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handling up to two LVDS input streams and up to two digital CMOS/TTL outputs.
|
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|
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Single or dual operation mode, output data mapping and DDR output modes are
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configured through input signals and the chip does not expose any control bus.
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Required properties:
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- compatible: Shall be "thine,thc63lvd1024"
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- vcc-supply: Power supply for TTL output, TTL CLOCKOUT signal, LVDS input,
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PPL and digital circuitry
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Optional properties:
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- powerdown-gpios: Power down GPIO signal, pin name "/PDWN". Active low
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- oe-gpios: Output enable GPIO signal, pin name "OE". Active high
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The THC63LVD1024 video port connections are modeled according
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to OF graph bindings specified by Documentation/devicetree/bindings/graph.txt
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Required video port nodes:
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- port@0: First LVDS input port
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- port@2: First digital CMOS/TTL parallel output
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Optional video port nodes:
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- port@1: Second LVDS input port
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- port@3: Second digital CMOS/TTL parallel output
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|
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Example:
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--------
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thc63lvd1024: lvds-decoder {
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compatible = "thine,thc63lvd1024";
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|
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vcc-supply = <®_lvds_vcc>;
|
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powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
|
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|
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
|
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|
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lvds_dec_in_0: endpoint {
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remote-endpoint = <&lvds_out>;
|
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};
|
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};
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|
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port@2{
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reg = <2>;
|
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|
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lvds_dec_out_2: endpoint {
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remote-endpoint = <&adv7511_in>;
|
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};
|
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};
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};
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};
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@@ -19,7 +19,8 @@ Required properties:
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clock-names property.
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- clock-names: list of clock names sorted in the same order as the clocks
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property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
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"aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
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"aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x",
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"aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk",
|
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"sclk_decon_eclk"
|
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- ports: contains a port which is connected to mic node. address-cells and
|
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size-cells must 1 and 0, respectively.
|
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@@ -34,10 +35,14 @@ decon: decon@13800000 {
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clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
|
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<&cmu_disp CLK_ACLK_XIU_DECON0X>,
|
||||
<&cmu_disp CLK_PCLK_SMMU_DECON0X>,
|
||||
<&cmu_disp CLK_ACLK_SMMU_DECON1X>,
|
||||
<&cmu_disp CLK_ACLK_XIU_DECON1X>,
|
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<&cmu_disp CLK_PCLK_SMMU_DECON1X>,
|
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<&cmu_disp CLK_SCLK_DECON_VCLK>,
|
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<&cmu_disp CLK_SCLK_DECON_ECLK>;
|
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clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x",
|
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"pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk";
|
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"pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x",
|
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"pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk";
|
||||
interrupt-names = "vsync", "lcd_sys";
|
||||
interrupts = <0 202 0>, <0 203 0>;
|
||||
|
||||
|
||||
@@ -13,6 +13,7 @@ Required Properties:
|
||||
- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
|
||||
- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
|
||||
- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
|
||||
- "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU
|
||||
- "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
|
||||
- "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
|
||||
|
||||
@@ -47,20 +48,21 @@ bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||
The following table lists for each supported model the port number
|
||||
corresponding to each DU output.
|
||||
|
||||
Port0 Port1 Port2 Port3
|
||||
Port0 Port1 Port2 Port3
|
||||
-----------------------------------------------------------------------------
|
||||
R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -
|
||||
R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
|
||||
R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
|
||||
R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
|
||||
R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
|
||||
R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - -
|
||||
R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - -
|
||||
R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
|
||||
R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
|
||||
R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
|
||||
R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
|
||||
R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
|
||||
R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -
|
||||
R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
|
||||
R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
|
||||
R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
|
||||
R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
|
||||
R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - -
|
||||
R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - -
|
||||
R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
|
||||
R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
|
||||
R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
|
||||
R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 -
|
||||
R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
|
||||
R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
|
||||
|
||||
|
||||
Example: R8A7795 (R-Car H3) ES2.0 DU
|
||||
|
||||
93
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
Archivo normal
93
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
Archivo normal
@@ -0,0 +1,93 @@
|
||||
Allwinner A31 DSI Encoder
|
||||
=========================
|
||||
|
||||
The DSI pipeline consists of two separate blocks: the DSI controller
|
||||
itself, and its associated D-PHY.
|
||||
|
||||
DSI Encoder
|
||||
-----------
|
||||
|
||||
The DSI Encoder generates the DSI signal from the TCON's.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun6i-a31-mipi-dsi
|
||||
- reg: base address and size of memory-mapped region
|
||||
- interrupts: interrupt associated to this IP
|
||||
- clocks: phandles to the clocks feeding the DSI encoder
|
||||
* bus: the DSI interface clock
|
||||
* mod: the DSI module clock
|
||||
- clock-names: the clock names mentioned above
|
||||
- phys: phandle to the D-PHY
|
||||
- phy-names: must be "dphy"
|
||||
- resets: phandle to the reset controller driving the encoder
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoint, usually coming from the
|
||||
associated TCON.
|
||||
|
||||
Any MIPI-DSI device attached to this should be described according to
|
||||
the bindings defined in ../mipi-dsi-bus.txt
|
||||
|
||||
D-PHY
|
||||
-----
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun6i-a31-mipi-dphy
|
||||
- reg: base address and size of memory-mapped region
|
||||
- clocks: phandles to the clocks feeding the DSI encoder
|
||||
* bus: the DSI interface clock
|
||||
* mod: the DSI module clock
|
||||
- clock-names: the clock names mentioned above
|
||||
- resets: phandle to the reset controller driving the encoder
|
||||
|
||||
Example:
|
||||
|
||||
dsi0: dsi@1ca0000 {
|
||||
compatible = "allwinner,sun6i-a31-mipi-dsi";
|
||||
reg = <0x01ca0000 0x1000>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MIPI_DSI>,
|
||||
<&ccu CLK_DSI_SCLK>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_MIPI_DSI>;
|
||||
phys = <&dphy0>;
|
||||
phy-names = "dphy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
|
||||
reg = <0>;
|
||||
power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */
|
||||
reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
|
||||
backlight = <&pwm_bl>;
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
dsi0_in_tcon0: endpoint {
|
||||
remote-endpoint = <&tcon0_out_dsi0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dphy0: d-phy@1ca1000 {
|
||||
compatible = "allwinner,sun6i-a31-mipi-dphy";
|
||||
reg = <0x01ca1000 0x1000>;
|
||||
clocks = <&ccu CLK_BUS_MIPI_DSI>,
|
||||
<&ccu CLK_DSI_DPHY>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_MIPI_DSI>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
28
Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.txt
Archivo normal
28
Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.txt
Archivo normal
@@ -0,0 +1,28 @@
|
||||
Broadcom V3D GPU
|
||||
|
||||
Only the Broadcom V3D 3.x and newer GPUs are covered by this binding.
|
||||
For V3D 2.x, see brcm,bcm-vc4.txt.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "brcm,7268-v3d" or "brcm,7278-v3d"
|
||||
- reg: Physical base addresses and lengths of the register areas
|
||||
- reg-names: Names for the register areas. The "hub", "bridge", and "core0"
|
||||
register areas are always required. The "gca" register area
|
||||
is required if the GCA cache controller is present.
|
||||
- interrupts: The interrupt numbers. The first interrupt is for the hub,
|
||||
while the following interrupts are for the cores.
|
||||
See bindings/interrupt-controller/interrupts.txt
|
||||
|
||||
Optional properties:
|
||||
- clocks: The core clock the unit runs on
|
||||
|
||||
v3d {
|
||||
compatible = "brcm,7268-v3d";
|
||||
reg = <0xf1204000 0x100>,
|
||||
<0xf1200000 0x4000>,
|
||||
<0xf1208000 0x4000>,
|
||||
<0xf1204100 0x100>;
|
||||
reg-names = "bridge", "hub", "core0", "gca";
|
||||
interrupts = <0 78 4>,
|
||||
<0 77 4>;
|
||||
};
|
||||
27
Documentation/devicetree/bindings/gpu/samsung-scaler.txt
Archivo normal
27
Documentation/devicetree/bindings/gpu/samsung-scaler.txt
Archivo normal
@@ -0,0 +1,27 @@
|
||||
* Samsung Exynos Image Scaler
|
||||
|
||||
Required properties:
|
||||
- compatible : value should be one of the following:
|
||||
(a) "samsung,exynos5420-scaler" for Scaler IP in Exynos5420
|
||||
(b) "samsung,exynos5433-scaler" for Scaler IP in Exynos5433
|
||||
|
||||
- reg : Physical base address of the IP registers and length of memory
|
||||
mapped region.
|
||||
|
||||
- interrupts : Interrupt specifier for scaler interrupt, according to format
|
||||
specific to interrupt parent.
|
||||
|
||||
- clocks : Clock specifier for scaler clock, according to generic clock
|
||||
bindings. (See Documentation/devicetree/bindings/clock/exynos*.txt)
|
||||
|
||||
- clock-names : Names of clocks. For exynos scaler, it should be "mscl"
|
||||
on 5420 and "pclk", "aclk" and "aclk_xiu" on 5433.
|
||||
|
||||
Example:
|
||||
scaler@12800000 {
|
||||
compatible = "samsung,exynos5420-scaler";
|
||||
reg = <0x12800000 0x1294>;
|
||||
interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_MSCL0>;
|
||||
clock-names = "mscl";
|
||||
};
|
||||
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Block a user