Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 CPU feature updates from Thomas Gleixner:
"Updates for x86 CPU features:
- Support for UMWAIT/UMONITOR, which allows to use MWAIT and MONITOR
instructions in user space to save power e.g. in HPC workloads
which spin wait on synchronization points.
The maximum time a MWAIT can halt in userspace is controlled by the
kernel and can be adjusted by the sysadmin.
- Speed up the MTRR handling code on CPUs which support cache
self-snooping correctly.
On those CPUs the wbinvd() invocations can be omitted which speeds
up the MTRR setup by a factor of 50.
- Support for the new x86 vendor Zhaoxin who develops processors
based on the VIA Centaur technology.
- Prevent 'cat /proc/cpuinfo' from affecting isolated NOHZ_FULL CPUs
by sending IPIs to retrieve the CPU frequency and use the cached
values instead.
- The addition and late revert of the FSGSBASE support. The revert
was required as it turned out that the code still has hard to
diagnose issues. Yet another engineering trainwreck...
- Small fixes, cleanups, improvements and the usual new Intel CPU
family/model addons"
* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (41 commits)
x86/fsgsbase: Revert FSGSBASE support
selftests/x86/fsgsbase: Fix some test case bugs
x86/entry/64: Fix and clean up paranoid_exit
x86/entry/64: Don't compile ignore_sysret if 32-bit emulation is enabled
selftests/x86: Test SYSCALL and SYSENTER manually with TF set
x86/mtrr: Skip cache flushes on CPUs with cache self-snooping
x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata
Documentation/ABI: Document umwait control sysfs interfaces
x86/umwait: Add sysfs interface to control umwait maximum time
x86/umwait: Add sysfs interface to control umwait C0.2 state
x86/umwait: Initialize umwait control values
x86/cpufeatures: Enumerate user wait instructions
x86/cpu: Disable frequency requests via aperfmperf IPI for nohz_full CPUs
x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3
ACPI, x86: Add Zhaoxin processors support for NONSTOP TSC
x86/cpu: Create Zhaoxin processors architecture support file
x86/cpu: Split Tremont based Atoms from the rest
Documentation/x86/64: Add documentation for GS/FS addressing mode
x86/elf: Enumerate kernel FSGSBASE capability in AT_HWCAP2
x86/cpu: Enable FSGSBASE on 64bit by default and add a chicken bit
...
This commit is contained in:
Linus Torvalds
@@ -22,8 +22,8 @@ enum cpuid_leafs
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CPUID_LNX_3,
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CPUID_7_0_EBX,
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CPUID_D_1_EAX,
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CPUID_F_0_EDX,
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CPUID_F_1_EDX,
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CPUID_LNX_4,
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CPUID_7_1_EAX,
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CPUID_8000_0008_EBX,
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CPUID_6_EAX,
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CPUID_8000_000A_EDX,
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@@ -239,12 +239,14 @@
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#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
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#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
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#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
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#define X86_FEATURE_FDP_EXCPTN_ONLY ( 9*32+ 6) /* "" FPU data pointer updated only on x87 exceptions */
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#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
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#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
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#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */
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#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
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#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
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#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
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#define X86_FEATURE_ZERO_FCS_FDS ( 9*32+13) /* "" Zero out FPU CS and FPU DS */
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#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
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#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */
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#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
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@@ -269,13 +271,19 @@
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#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */
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#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */
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/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */
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#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
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/*
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* Extended auxiliary flags: Linux defined - for features scattered in various
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* CPUID levels like 0xf, etc.
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*
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* Reuse free bits when adding new feature flags!
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*/
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#define X86_FEATURE_CQM_LLC (11*32+ 0) /* LLC QoS if 1 */
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#define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */
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#define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
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#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
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/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */
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#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring */
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#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */
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#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */
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/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
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/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
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#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
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@@ -322,6 +330,7 @@
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#define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */
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#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
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#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
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#define X86_FEATURE_WAITPKG (16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
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#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
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#define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */
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#define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */
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@@ -56,6 +56,7 @@
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#define INTEL_FAM6_ICELAKE_XEON_D 0x6C
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#define INTEL_FAM6_ICELAKE_DESKTOP 0x7D
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#define INTEL_FAM6_ICELAKE_MOBILE 0x7E
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#define INTEL_FAM6_ICELAKE_NNPI 0x9D
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/* "Small Core" Processors (Atom) */
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@@ -76,6 +77,7 @@
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#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
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#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
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#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
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#define INTEL_FAM6_ATOM_TREMONT_X 0x86 /* Jacobsville */
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/* Xeon Phi */
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@@ -61,6 +61,15 @@
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#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
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#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
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#define MSR_IA32_UMWAIT_CONTROL 0xe1
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#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
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#define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1)
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/*
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* The time field is bit[31:2], but representing a 32bit value with
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* bit[1:0] zero.
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*/
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#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
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#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
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#define NHM_C3_AUTO_DEMOTE (1UL << 25)
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#define NHM_C1_AUTO_DEMOTE (1UL << 26)
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@@ -144,7 +144,8 @@ enum cpuid_regs_idx {
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NSC 8
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#define X86_VENDOR_HYGON 9
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#define X86_VENDOR_NUM 10
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#define X86_VENDOR_ZHAOXIN 10
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#define X86_VENDOR_NUM 11
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#define X86_VENDOR_UNKNOWN 0xff
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