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MIPS: Loongson1C: Add board support

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Adds basic platform devices for Loongson1C, including serial port
and ethernet.

Signed-off-by: Yang Ling <gnaygnil@gmail.com>
Cc: keguang.zhang@gmail.com
Cc: chenhc@lemote.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13304/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Yang Ling
2016-05-19 12:29:30 +08:00
committed by Ralf Baechle
parent a1ca83869d
commit 12e3280b33
13 changed files with 283 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
arch/mips/include/asm/mach-loongson32/irq.h
View File

@@ -36,9 +36,14 @@
#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
#if defined(CONFIG_LOONGSON1_LS1B)
#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
#elif defined(CONFIG_LOONGSON1_LS1C)
#define LS1X_UART1_IRQ LS1X_IRQ(0, 4)
#define LS1X_UART2_IRQ LS1X_IRQ(0, 5)
#endif
#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
@@ -47,6 +52,9 @@
#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
#if defined(CONFIG_LOONGSON1_LS1C)
#define LS1X_NAND_IRQ LS1X_IRQ(0, 16)
#endif
#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
@@ -54,18 +62,49 @@
#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
#if defined(CONFIG_LOONGSON1_LS1B)
#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
#define LS1X_UART4_IRQ LS1X_IRQ(0, 29)
#define LS1X_UART5_IRQ LS1X_IRQ(0, 30)
#elif defined(CONFIG_LOONGSON1_LS1C)
#define LS1X_UART3_IRQ LS1X_IRQ(0, 29)
#define LS1X_ADC_IRQ LS1X_IRQ(0, 30)
#define LS1X_SDIO_IRQ LS1X_IRQ(0, 31)
#endif
#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
#if defined(CONFIG_LOONGSON1_LS1B)
#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
#elif defined(CONFIG_LOONGSON1_LS1C)
#define LS1X_OTG_IRQ LS1X_IRQ(1, 2)
#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 3)
#define LS1X_CAM_IRQ LS1X_IRQ(1, 4)
#define LS1X_UART4_IRQ LS1X_IRQ(1, 5)
#define LS1X_UART5_IRQ LS1X_IRQ(1, 6)
#define LS1X_UART6_IRQ LS1X_IRQ(1, 7)
#define LS1X_UART7_IRQ LS1X_IRQ(1, 8)
#define LS1X_UART8_IRQ LS1X_IRQ(1, 9)
#define LS1X_UART9_IRQ LS1X_IRQ(1, 13)
#define LS1X_UART10_IRQ LS1X_IRQ(1, 14)
#define LS1X_UART11_IRQ LS1X_IRQ(1, 15)
#define LS1X_I2C0_IRQ LS1X_IRQ(1, 17)
#define LS1X_I2C1_IRQ LS1X_IRQ(1, 18)
#define LS1X_I2C2_IRQ LS1X_IRQ(1, 19)
#endif
#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE)
#if defined(CONFIG_LOONGSON1_LS1B)
#define INTN 4
#elif defined(CONFIG_LOONGSON1_LS1C)
#define INTN 5
#endif
#define LS1X_IRQS (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE)
#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)

5
arch/mips/include/asm/mach-loongson32/loongson1.h
View File

@@ -12,7 +12,11 @@
#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
#define __ASM_MACH_LOONGSON32_LOONGSON1_H
#if defined(CONFIG_LOONGSON1_LS1B)
#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
#elif defined(CONFIG_LOONGSON1_LS1C)
#define DEFAULT_MEMSIZE 32
#endif
/* Loongson 1 Register Bases */
#define LS1X_MUX_BASE 0x1fd00420
@@ -20,6 +24,7 @@
#define LS1X_GPIO0_BASE 0x1fd010c0
#define LS1X_GPIO1_BASE 0x1fd010c4
#define LS1X_DMAC_BASE 0x1fd01160
#define LS1X_CBUS_BASE 0x1fd011c0
#define LS1X_EHCI_BASE 0x1fe00000
#define LS1X_OHCI_BASE 0x1fe08000
#define LS1X_GMAC0_BASE 0x1fe10000

34
arch/mips/include/asm/mach-loongson32/regs-clk.h
View File

@@ -18,6 +18,7 @@
#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
#if defined(CONFIG_LOONGSON1_LS1B)
/* Clock PLL Divisor Register Bits */
#define DIV_DC_EN BIT(31)
#define DIV_DC_RST BIT(30)
@@ -48,4 +49,37 @@
#define BYPASS_DDR_WIDTH 1
#define BYPASS_CPU_WIDTH 1
#elif defined(CONFIG_LOONGSON1_LS1C)
/* PLL/SDRAM Frequency configuration register Bits */
#define PLL_VALID BIT(31)
#define FRAC_N GENMASK(23, 16)
#define RST_TIME GENMASK(3, 2)
#define SDRAM_DIV GENMASK(1, 0)
/* CPU/CAMERA/DC Frequency configuration register Bits */
#define DIV_DC_EN BIT(31)
#define DIV_DC GENMASK(30, 24)
#define DIV_CAM_EN BIT(23)
#define DIV_CAM GENMASK(22, 16)
#define DIV_CPU_EN BIT(15)
#define DIV_CPU GENMASK(14, 8)
#define DIV_DC_SEL_EN BIT(5)
#define DIV_DC_SEL BIT(4)
#define DIV_CAM_SEL_EN BIT(3)
#define DIV_CAM_SEL BIT(2)
#define DIV_CPU_SEL_EN BIT(1)
#define DIV_CPU_SEL BIT(0)
#define DIV_DC_SHIFT 24
#define DIV_CAM_SHIFT 16
#define DIV_CPU_SHIFT 8
#define DIV_DDR_SHIFT 0
#define DIV_DC_WIDTH 7
#define DIV_CAM_WIDTH 7
#define DIV_CPU_WIDTH 7
#define DIV_DDR_WIDTH 2
#endif
#endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */

61
arch/mips/include/asm/mach-loongson32/regs-mux.h
View File

@@ -18,6 +18,7 @@
#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0)
#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4)
#if defined(CONFIG_LOONGSON1_LS1B)
/* MUX CTRL0 Register Bits */
#define UART0_USE_PWM23 BIT(28)
#define UART0_USE_PWM01 BIT(27)
@@ -64,4 +65,64 @@
#define GMAC1_USE_PWM23 BIT(1)
#define GMAC0_USE_PWM01 BIT(0)
#elif defined(CONFIG_LOONGSON1_LS1C)
/* SHUT_CTRL Register Bits */
#define UART_SPLIT GENMASK(31, 30)
#define OUTPUT_CLK GENMASK(29, 26)
#define ADC_SHUT BIT(25)
#define SDIO_SHUT BIT(24)
#define DMA2_SHUT BIT(23)
#define DMA1_SHUT BIT(22)
#define DMA0_SHUT BIT(21)
#define SPI1_SHUT BIT(20)
#define SPI0_SHUT BIT(19)
#define I2C2_SHUT BIT(18)
#define I2C1_SHUT BIT(17)
#define I2C0_SHUT BIT(16)
#define AC97_SHUT BIT(15)
#define I2S_SHUT BIT(14)
#define UART3_SHUT BIT(13)
#define UART2_SHUT BIT(12)
#define UART1_SHUT BIT(11)
#define UART0_SHUT BIT(10)
#define CAN1_SHUT BIT(9)
#define CAN0_SHUT BIT(8)
#define ECC_SHUT BIT(7)
#define GMAC_SHUT BIT(6)
#define USBHOST_SHUT BIT(5)
#define USBOTG_SHUT BIT(4)
#define SDRAM_SHUT BIT(3)
#define SRAM_SHUT BIT(2)
#define CAM_SHUT BIT(1)
#define LCD_SHUT BIT(0)
#define UART_SPLIT_SHIFT 30
#define OUTPUT_CLK_SHIFT 26
/* MISC_CTRL Register Bits */
#define USBHOST_RSTN BIT(31)
#define PHY_INTF_SELI GENMASK(30, 28)
#define AC97_EN BIT(25)
#define SDIO_DMA_EN GENMASK(24, 23)
#define ADC_DMA_EN BIT(22)
#define SDIO_USE_SPI1 BIT(17)
#define SDIO_USE_SPI0 BIT(16)
#define SRAM_CTRL GENMASK(15, 0)
#define PHY_INTF_SELI_SHIFT 28
#define SDIO_DMA_EN_SHIFT 23
#define SRAM_CTRL_SHIFT 0
#define LS1X_CBUS_REG(n, x) \
((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x)))
#define LS1X_CBUS_FIRST(n) LS1X_CBUS_REG(n, 0x00)
#define LS1X_CBUS_SECOND(n) LS1X_CBUS_REG(n, 0x10)
#define LS1X_CBUS_THIRD(n) LS1X_CBUS_REG(n, 0x20)
#define LS1X_CBUS_FOURTHT(n) LS1X_CBUS_REG(n, 0x30)
#define LS1X_CBUS_FIFTHT(n) LS1X_CBUS_REG(n, 0x40)
#endif
#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */