crypto: ccp - Base AXI DMA cache settings on device tree
The default cache operations for ARM64 were changed during 3.15. To use coherent operations a "dma-coherent" device tree property is required. If that property is not present in the device tree node then the non-coherent operations are assigned for the device. Add support to the ccp driver to assign the AXI DMA cache settings based on whether the "dma-coherent" property is present in the device node. If present, use settings that work with the caches. If not present, use settings that do not look at the caches. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@@ -30,6 +30,7 @@
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#define TRNG_RETRIES 10
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#define CACHE_NONE 0x00
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#define CACHE_WB_NO_ALLOC 0xb7
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@@ -255,6 +256,9 @@ struct ccp_device {
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/* Suspend support */
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unsigned int suspending;
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wait_queue_head_t suspend_queue;
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/* DMA caching attribute support */
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unsigned int axcache;
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};
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