dt-binding: cpu-topology: Move cpu-map to a common binding.
cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found here. https://lkml.org/lkml/2018/11/6/19 Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
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Atish Patra
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Paul Walmsley
Paul Walmsley
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553
Documentation/devicetree/bindings/cpu/cpu-topology.txt
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553
Documentation/devicetree/bindings/cpu/cpu-topology.txt
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===========================================
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CPU topology binding description
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===========================================
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===========================================
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1 - Introduction
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===========================================
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In a SMP system, the hierarchy of CPUs is defined through three entities that
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are used to describe the layout of physical CPUs in the system:
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- socket
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- cluster
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- core
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- thread
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The bottom hierarchy level sits at core or thread level depending on whether
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symmetric multi-threading (SMT) is supported or not.
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For instance in a system where CPUs support SMT, "cpu" nodes represent all
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threads existing in the system and map to the hierarchy level "thread" above.
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In systems where SMT is not supported "cpu" nodes represent all cores present
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in the system and map to the hierarchy level "core" above.
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CPU topology bindings allow one to associate cpu nodes with hierarchical groups
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corresponding to the system hierarchy; syntactically they are defined as device
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tree nodes.
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Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
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used for any other architecture as well.
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The cpu nodes, as per bindings defined in [4], represent the devices that
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correspond to physical CPUs and are to be mapped to the hierarchy levels.
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A topology description containing phandles to cpu nodes that are not compliant
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with bindings standardized in [4] is therefore considered invalid.
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===========================================
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2 - cpu-map node
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===========================================
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The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
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child of the cpus node and provides a container where the actual topology
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nodes are listed.
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- cpu-map node
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Usage: Optional - On SMP systems provide CPUs topology to the OS.
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Uniprocessor systems do not require a topology
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description and therefore should not define a
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cpu-map node.
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Description: The cpu-map node is just a container node where its
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subnodes describe the CPU topology.
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Node name must be "cpu-map".
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The cpu-map node's parent node must be the cpus node.
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The cpu-map node's child nodes can be:
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- one or more cluster nodes or
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- one or more socket nodes in a multi-socket system
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Any other configuration is considered invalid.
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The cpu-map node can only contain 4 types of child nodes:
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- socket node
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- cluster node
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- core node
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- thread node
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whose bindings are described in paragraph 3.
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The nodes describing the CPU topology (socket/cluster/core/thread) can
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only be defined within the cpu-map node and every core/thread in the
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system must be defined within the topology. Any other configuration is
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invalid and therefore must be ignored.
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===========================================
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2.1 - cpu-map child nodes naming convention
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===========================================
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cpu-map child nodes must follow a naming convention where the node name
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must be "socketN", "clusterN", "coreN", "threadN" depending on the node type
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(ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
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which are siblings within a single common parent node must be given a unique and
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sequential N value, starting from 0).
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cpu-map child nodes which do not share a common parent node can have the same
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name (ie same number N as other cpu-map child nodes at different device tree
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levels) since name uniqueness will be guaranteed by the device tree hierarchy.
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===========================================
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3 - socket/cluster/core/thread node bindings
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===========================================
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Bindings for socket/cluster/cpu/thread nodes are defined as follows:
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- socket node
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Description: must be declared within a cpu-map node, one node
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per physical socket in the system. A system can
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contain single or multiple physical socket.
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The association of sockets and NUMA nodes is beyond
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the scope of this bindings, please refer [2] for
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NUMA bindings.
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This node is optional for a single socket system.
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The socket node name must be "socketN" as described in 2.1 above.
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A socket node can not be a leaf node.
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A socket node's child nodes must be one or more cluster nodes.
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Any other configuration is considered invalid.
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- cluster node
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Description: must be declared within a cpu-map node, one node
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per cluster. A system can contain several layers of
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clustering within a single physical socket and cluster
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nodes can be contained in parent cluster nodes.
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The cluster node name must be "clusterN" as described in 2.1 above.
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A cluster node can not be a leaf node.
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A cluster node's child nodes must be:
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- one or more cluster nodes; or
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- one or more core nodes
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Any other configuration is considered invalid.
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- core node
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Description: must be declared in a cluster node, one node per core in
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the cluster. If the system does not support SMT, core
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nodes are leaf nodes, otherwise they become containers of
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thread nodes.
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The core node name must be "coreN" as described in 2.1 above.
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A core node must be a leaf node if SMT is not supported.
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Properties for core nodes that are leaf nodes:
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- cpu
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Usage: required
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Value type: <phandle>
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Definition: a phandle to the cpu node that corresponds to the
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core node.
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If a core node is not a leaf node (CPUs supporting SMT) a core node's
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child nodes can be:
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- one or more thread nodes
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Any other configuration is considered invalid.
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- thread node
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Description: must be declared in a core node, one node per thread
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in the core if the system supports SMT. Thread nodes are
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always leaf nodes in the device tree.
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The thread node name must be "threadN" as described in 2.1 above.
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A thread node must be a leaf node.
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A thread node must contain the following property:
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- cpu
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Usage: required
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Value type: <phandle>
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Definition: a phandle to the cpu node that corresponds to
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the thread node.
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===========================================
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4 - Example dts
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===========================================
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Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single
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physical socket):
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cpus {
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#size-cells = <0>;
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#address-cells = <2>;
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cpu-map {
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socket0 {
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cluster0 {
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cluster0 {
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core0 {
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thread0 {
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cpu = <&CPU0>;
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};
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thread1 {
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cpu = <&CPU1>;
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};
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};
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core1 {
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thread0 {
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cpu = <&CPU2>;
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};
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thread1 {
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cpu = <&CPU3>;
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};
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};
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};
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cluster1 {
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core0 {
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thread0 {
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cpu = <&CPU4>;
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};
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thread1 {
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cpu = <&CPU5>;
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};
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};
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core1 {
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thread0 {
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cpu = <&CPU6>;
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};
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thread1 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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cluster1 {
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cluster0 {
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core0 {
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thread0 {
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cpu = <&CPU8>;
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};
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thread1 {
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cpu = <&CPU9>;
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};
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};
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core1 {
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thread0 {
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cpu = <&CPU10>;
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};
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thread1 {
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cpu = <&CPU11>;
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};
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};
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};
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cluster1 {
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core0 {
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thread0 {
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cpu = <&CPU12>;
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};
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thread1 {
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cpu = <&CPU13>;
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};
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};
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core1 {
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thread0 {
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cpu = <&CPU14>;
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};
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thread1 {
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cpu = <&CPU15>;
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};
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};
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};
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};
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};
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU4: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10000>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU5: cpu@10001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10001>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU6: cpu@10100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU7: cpu@10101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU8: cpu@100000000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU9: cpu@100000001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU10: cpu@100000100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU11: cpu@100000101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU12: cpu@100010000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x10000>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU13: cpu@100010001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x10001>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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CPU14: cpu@100010100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x10100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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|
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CPU15: cpu@100010101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
|
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reg = <0x1 0x10101>;
|
||||
enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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};
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Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT):
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|
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
|
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|
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
|
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cpu = <&CPU1>;
|
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};
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core2 {
|
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cpu = <&CPU2>;
|
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};
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core3 {
|
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cpu = <&CPU3>;
|
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};
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||||
};
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cluster1 {
|
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core0 {
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cpu = <&CPU4>;
|
||||
};
|
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core1 {
|
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cpu = <&CPU5>;
|
||||
};
|
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core2 {
|
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cpu = <&CPU6>;
|
||||
};
|
||||
core3 {
|
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cpu = <&CPU7>;
|
||||
};
|
||||
};
|
||||
};
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CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
};
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||||
|
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CPU2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
CPU4: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
CPU5: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
};
|
||||
|
||||
CPU6: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
};
|
||||
|
||||
CPU7: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
};
|
||||
};
|
||||
|
||||
Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system)
|
||||
|
||||
{
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "sifive,fu540g", "sifive,fu500";
|
||||
model = "sifive,hifive-unleashed-a00";
|
||||
|
||||
...
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu-map {
|
||||
socket0 {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
core2 {
|
||||
cpu0 = <&CPU2>;
|
||||
};
|
||||
core3 {
|
||||
cpu0 = <&CPU3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
reg = <0x1>;
|
||||
}
|
||||
|
||||
CPU2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
reg = <0x2>;
|
||||
}
|
||||
CPU3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
reg = <0x3>;
|
||||
}
|
||||
CPU4: cpu@4 {
|
||||
device_type = "cpu";
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
reg = <0x4>;
|
||||
}
|
||||
}
|
||||
};
|
||||
===============================================================================
|
||||
[1] ARM Linux kernel documentation
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml
|
||||
[2] Devicetree NUMA binding description
|
||||
Documentation/devicetree/bindings/numa.txt
|
||||
[3] RISC-V Linux kernel documentation
|
||||
Documentation/devicetree/bindings/riscv/cpus.txt
|
||||
[4] https://www.devicetree.org/specifications/
|
||||
Reference in New Issue
Block a user