Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (106 commits) powerpc/p3060qds: Add support for P3060QDS board powerpc/83xx: Add shutdown request support to MCU handling on MPC8349 MITX powerpc/85xx: Make kexec to interate over online cpus powerpc/fsl_booke: Fix comment in head_fsl_booke.S powerpc/85xx: issue 15 EOI after core reset for FSL CoreNet devices powerpc/8xxx: Fix interrupt handling in MPC8xxx GPIO driver powerpc/85xx: Add 'fsl,pq3-gpio' compatiable for GPIO driver powerpc/86xx: Correct Gianfar support for GE boards powerpc/cpm: Clear muram before it is in use. drivers/virt: add ioctl for 32-bit compat on 64-bit to fsl-hv-manager powerpc/fsl_msi: add support for "msi-address-64" property powerpc/85xx: Setup secondary cores PIR with hard SMP id powerpc/fsl-booke: Fix settlbcam for 64-bit powerpc/85xx: Adding DCSR node to dtsi device trees powerpc/85xx: clean up FPGA device tree nodes for Freecsale QorIQ boards powerpc/85xx: fix PHYS_64BIT selection for P1022DS powerpc/fsl-booke: Fix setup_initial_memory_limit to not blindly map powerpc: respect mem= setting for early memory limit setup powerpc: Update corenet64_smp_defconfig powerpc: Update mpc85xx/corenet 32-bit defconfigs ... Fix up trivial conflicts in: - arch/powerpc/configs/40x/hcu4_defconfig removed stale file, edited elsewhere - arch/powerpc/include/asm/udbg.h, arch/powerpc/kernel/udbg.c: added opal and gelic drivers vs added ePAPR driver - drivers/tty/serial/8250.c moved UPIO_TSI to powerpc vs removed UPIO_DWAPB support
此提交包含在：
Linus Torvalds
@@ -99,6 +99,14 @@ config GPIO_MPC5200
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def_bool y
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depends on PPC_MPC52xx
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config GPIO_MPC8XXX
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bool "MPC512x/MPC8xxx GPIO support"
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depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \
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FSL_SOC_BOOKE || PPC_86xx
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help
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Say Y here if you're going to use hardware that connects to the
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MPC512x/831x/834x/837x/8572/8610 GPIOs.
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config GPIO_MSM_V1
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tristate "Qualcomm MSM GPIO v1"
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depends on GPIOLIB && ARCH_MSM
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@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o
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obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o
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obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o
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obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o
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obj-$(CONFIG_GPIO_MPC8XXX) += gpio-mpc8xxx.o
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obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o
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obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
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obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
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398
drivers/gpio/gpio-mpc8xxx.c
一般檔案
398
drivers/gpio/gpio-mpc8xxx.c
一般檔案
@@ -0,0 +1,398 @@
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/*
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* GPIOs on MPC512x/8349/8572/8610 and compatible
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*
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* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#define MPC8XXX_GPIO_PINS 32
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#define GPIO_DIR 0x00
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#define GPIO_ODR 0x04
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#define GPIO_DAT 0x08
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#define GPIO_IER 0x0c
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#define GPIO_IMR 0x10
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#define GPIO_ICR 0x14
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#define GPIO_ICR2 0x18
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struct mpc8xxx_gpio_chip {
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struct of_mm_gpio_chip mm_gc;
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spinlock_t lock;
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/*
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* shadowed data register to be able to clear/set output pins in
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* open drain mode safely
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*/
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u32 data;
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struct irq_host *irq;
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void *of_dev_id_data;
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};
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static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
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{
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return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
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}
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static inline struct mpc8xxx_gpio_chip *
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to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
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{
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return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
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}
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static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
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}
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/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
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* defined as output cannot be determined by reading GPDAT register,
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* so we use shadow data register instead. The status of input pins
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* is determined by reading GPDAT register.
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*/
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static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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u32 val;
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
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return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
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}
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static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
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}
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static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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if (val)
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mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
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else
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mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
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out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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return 0;
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}
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static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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unsigned long flags;
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mpc8xxx_gpio_set(gc, gpio, val);
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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return 0;
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}
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static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
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return irq_create_mapping(mpc8xxx_gc->irq, offset);
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else
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return -ENXIO;
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}
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static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned int mask;
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mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
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if (mask)
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generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
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32 - ffs(mask)));
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chip->irq_eoi(&desc->irq_data);
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}
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static void mpc8xxx_irq_unmask(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static void mpc8xxx_irq_mask(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static void mpc8xxx_irq_ack(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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}
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static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_ICR,
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mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_ICR,
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mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long gpio = irqd_to_hwirq(d);
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void __iomem *reg;
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unsigned int shift;
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unsigned long flags;
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if (gpio < 16) {
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reg = mm->regs + GPIO_ICR;
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shift = (15 - gpio) * 2;
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} else {
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reg = mm->regs + GPIO_ICR2;
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shift = (15 - (gpio % 16)) * 2;
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}
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrsetbits_be32(reg, 3 << shift, 2 << shift);
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrsetbits_be32(reg, 3 << shift, 1 << shift);
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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||||
|
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case IRQ_TYPE_EDGE_BOTH:
|
||||
spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
||||
clrbits32(reg, 3 << shift);
|
||||
spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip mpc8xxx_irq_chip = {
|
||||
.name = "mpc8xxx-gpio",
|
||||
.irq_unmask = mpc8xxx_irq_unmask,
|
||||
.irq_mask = mpc8xxx_irq_mask,
|
||||
.irq_ack = mpc8xxx_irq_ack,
|
||||
.irq_set_type = mpc8xxx_irq_set_type,
|
||||
};
|
||||
|
||||
static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
|
||||
|
||||
if (mpc8xxx_gc->of_dev_id_data)
|
||||
mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
|
||||
|
||||
irq_set_chip_data(virq, h->host_data);
|
||||
irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
|
||||
irq_set_irq_type(virq, IRQ_TYPE_NONE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct,
|
||||
const u32 *intspec, unsigned int intsize,
|
||||
irq_hw_number_t *out_hwirq,
|
||||
unsigned int *out_flags)
|
||||
|
||||
{
|
||||
/* interrupt sense values coming from the device tree equal either
|
||||
* EDGE_FALLING or EDGE_BOTH
|
||||
*/
|
||||
*out_hwirq = intspec[0];
|
||||
*out_flags = intspec[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
|
||||
.map = mpc8xxx_gpio_irq_map,
|
||||
.xlate = mpc8xxx_gpio_irq_xlate,
|
||||
};
|
||||
|
||||
static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
|
||||
{ .compatible = "fsl,mpc8349-gpio", },
|
||||
{ .compatible = "fsl,mpc8572-gpio", },
|
||||
{ .compatible = "fsl,mpc8610-gpio", },
|
||||
{ .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
|
||||
{ .compatible = "fsl,pq3-gpio", },
|
||||
{ .compatible = "fsl,qoriq-gpio", },
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init mpc8xxx_add_controller(struct device_node *np)
|
||||
{
|
||||
struct mpc8xxx_gpio_chip *mpc8xxx_gc;
|
||||
struct of_mm_gpio_chip *mm_gc;
|
||||
struct gpio_chip *gc;
|
||||
const struct of_device_id *id;
|
||||
unsigned hwirq;
|
||||
int ret;
|
||||
|
||||
mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
|
||||
if (!mpc8xxx_gc) {
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
spin_lock_init(&mpc8xxx_gc->lock);
|
||||
|
||||
mm_gc = &mpc8xxx_gc->mm_gc;
|
||||
gc = &mm_gc->gc;
|
||||
|
||||
mm_gc->save_regs = mpc8xxx_gpio_save_regs;
|
||||
gc->ngpio = MPC8XXX_GPIO_PINS;
|
||||
gc->direction_input = mpc8xxx_gpio_dir_in;
|
||||
gc->direction_output = mpc8xxx_gpio_dir_out;
|
||||
if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
|
||||
gc->get = mpc8572_gpio_get;
|
||||
else
|
||||
gc->get = mpc8xxx_gpio_get;
|
||||
gc->set = mpc8xxx_gpio_set;
|
||||
gc->to_irq = mpc8xxx_gpio_to_irq;
|
||||
|
||||
ret = of_mm_gpiochip_add(np, mm_gc);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
hwirq = irq_of_parse_and_map(np, 0);
|
||||
if (hwirq == NO_IRQ)
|
||||
goto skip_irq;
|
||||
|
||||
mpc8xxx_gc->irq =
|
||||
irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS,
|
||||
&mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS);
|
||||
if (!mpc8xxx_gc->irq)
|
||||
goto skip_irq;
|
||||
|
||||
id = of_match_node(mpc8xxx_gpio_ids, np);
|
||||
if (id)
|
||||
mpc8xxx_gc->of_dev_id_data = id->data;
|
||||
|
||||
mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
|
||||
|
||||
/* ack and mask all irqs */
|
||||
out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
|
||||
out_be32(mm_gc->regs + GPIO_IMR, 0);
|
||||
|
||||
irq_set_handler_data(hwirq, mpc8xxx_gc);
|
||||
irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
|
||||
|
||||
skip_irq:
|
||||
return;
|
||||
|
||||
err:
|
||||
pr_err("%s: registration failed with status %d\n",
|
||||
np->full_name, ret);
|
||||
kfree(mpc8xxx_gc);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static int __init mpc8xxx_add_gpiochips(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
for_each_matching_node(np, mpc8xxx_gpio_ids)
|
||||
mpc8xxx_add_controller(np);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(mpc8xxx_add_gpiochips);
|
||||
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