MIPS: Remove support for LASAT
All LASAT has probably gone bad, so let's remove Linux support. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer
@@ -13,7 +13,6 @@ obj-$(CONFIG_PCI_DRIVERS_GENERIC)+= pci-generic.o
|
||||
obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
|
||||
obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
|
||||
obj-$(CONFIG_MIPS_MSC) += ops-msc.o
|
||||
obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
|
||||
obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o
|
||||
obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
|
||||
obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
|
||||
@@ -31,7 +30,6 @@ obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xtalk-bridge.o
|
||||
# These are still pretty much in the old state, watch, go blind.
|
||||
#
|
||||
obj-$(CONFIG_ATH79) += fixup-ath79.o
|
||||
obj-$(CONFIG_LASAT) += pci-lasat.o
|
||||
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
|
||||
obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
|
||||
obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
|
||||
|
||||
@@ -1,136 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
#include <asm/lasat/lasat.h>
|
||||
#include <asm/nile4.h>
|
||||
|
||||
#define PCI_ACCESS_READ 0
|
||||
#define PCI_ACCESS_WRITE 1
|
||||
|
||||
#define LO(reg) (reg / 4)
|
||||
#define HI(reg) (reg / 4 + 1)
|
||||
|
||||
volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
|
||||
|
||||
static int nile4_pcibios_config_access(unsigned char access_type,
|
||||
struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
|
||||
{
|
||||
unsigned char busnum = bus->number;
|
||||
u32 adr, mask, err;
|
||||
|
||||
if ((busnum == 0) && (PCI_SLOT(devfn) > 8))
|
||||
/* The addressing scheme chosen leaves room for just
|
||||
* 8 devices on the first busnum (besides the PCI
|
||||
* controller itself) */
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) {
|
||||
/* Access controller registers directly */
|
||||
if (access_type == PCI_ACCESS_WRITE) {
|
||||
vrc_pciregs[(0x200 + where) >> 2] = *val;
|
||||
} else {
|
||||
*val = vrc_pciregs[(0x200 + where) >> 2];
|
||||
}
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
/* Temporarily map PCI Window 1 to config space */
|
||||
mask = vrc_pciregs[LO(NILE4_PCIINIT1)];
|
||||
vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0);
|
||||
|
||||
/* Clear PCI Error register. This also clears the Error Type
|
||||
* bits in the Control register */
|
||||
vrc_pciregs[LO(NILE4_PCIERR)] = 0;
|
||||
vrc_pciregs[HI(NILE4_PCIERR)] = 0;
|
||||
|
||||
/* Setup address */
|
||||
if (busnum == 0)
|
||||
adr =
|
||||
KSEG1ADDR(PCI_WINDOW1) +
|
||||
((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8)
|
||||
| (where & ~3));
|
||||
else
|
||||
adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) |
|
||||
(where & ~3);
|
||||
|
||||
if (access_type == PCI_ACCESS_WRITE)
|
||||
*(u32 *) adr = *val;
|
||||
else
|
||||
*val = *(u32 *) adr;
|
||||
|
||||
/* Check for master or target abort */
|
||||
err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7;
|
||||
|
||||
/* Restore PCI Window 1 */
|
||||
vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;
|
||||
|
||||
if (err)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 *val)
|
||||
{
|
||||
u32 data = 0;
|
||||
int err;
|
||||
|
||||
if ((size == 2) && (where & 1))
|
||||
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||
else if ((size == 4) && (where & 3))
|
||||
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||
|
||||
err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
|
||||
&data);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (size == 1)
|
||||
*val = (data >> ((where & 3) << 3)) & 0xff;
|
||||
else if (size == 2)
|
||||
*val = (data >> ((where & 3) << 3)) & 0xffff;
|
||||
else
|
||||
*val = data;
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 val)
|
||||
{
|
||||
u32 data = 0;
|
||||
int err;
|
||||
|
||||
if ((size == 2) && (where & 1))
|
||||
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||
else if ((size == 4) && (where & 3))
|
||||
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||
|
||||
err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
|
||||
&data);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (size == 1)
|
||||
data = (data & ~(0xff << ((where & 3) << 3))) |
|
||||
(val << ((where & 3) << 3));
|
||||
else if (size == 2)
|
||||
data = (data & ~(0xffff << ((where & 3) << 3))) |
|
||||
(val << ((where & 3) << 3));
|
||||
else
|
||||
data = val;
|
||||
|
||||
if (nile4_pcibios_config_access
|
||||
(PCI_ACCESS_WRITE, bus, devfn, where, &data))
|
||||
return -1;
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
struct pci_ops nile4_pci_ops = {
|
||||
.read = nile4_pcibios_read,
|
||||
.write = nile4_pcibios_write,
|
||||
};
|
||||
@@ -1,88 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2000, 2001, 04 Keith M Wesolowski
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/lasat/lasat.h>
|
||||
|
||||
#include <irq.h>
|
||||
|
||||
extern struct pci_ops nile4_pci_ops;
|
||||
extern struct pci_ops gt64xxx_pci0_ops;
|
||||
static struct resource lasat_pci_mem_resource = {
|
||||
.name = "LASAT PCI MEM",
|
||||
.start = 0x18000000,
|
||||
.end = 0x19ffffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct resource lasat_pci_io_resource = {
|
||||
.name = "LASAT PCI IO",
|
||||
.start = 0x1a000000,
|
||||
.end = 0x1bffffff,
|
||||
.flags = IORESOURCE_IO,
|
||||
};
|
||||
|
||||
static struct pci_controller lasat_pci_controller = {
|
||||
.mem_resource = &lasat_pci_mem_resource,
|
||||
.io_resource = &lasat_pci_io_resource,
|
||||
};
|
||||
|
||||
static int __init lasat_pci_setup(void)
|
||||
{
|
||||
printk(KERN_DEBUG "PCI: starting\n");
|
||||
|
||||
if (IS_LASAT_200())
|
||||
lasat_pci_controller.pci_ops = &nile4_pci_ops;
|
||||
else
|
||||
lasat_pci_controller.pci_ops = >64xxx_pci0_ops;
|
||||
|
||||
register_pci_controller(&lasat_pci_controller);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(lasat_pci_setup);
|
||||
|
||||
#define LASAT_IRQ_ETH1 (LASAT_IRQ_BASE + 0)
|
||||
#define LASAT_IRQ_ETH0 (LASAT_IRQ_BASE + 1)
|
||||
#define LASAT_IRQ_HDC (LASAT_IRQ_BASE + 2)
|
||||
#define LASAT_IRQ_COMP (LASAT_IRQ_BASE + 3)
|
||||
#define LASAT_IRQ_HDLC (LASAT_IRQ_BASE + 4)
|
||||
#define LASAT_IRQ_PCIA (LASAT_IRQ_BASE + 5)
|
||||
#define LASAT_IRQ_PCIB (LASAT_IRQ_BASE + 6)
|
||||
#define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7)
|
||||
#define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8)
|
||||
|
||||
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
switch (slot) {
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
return LASAT_IRQ_PCIA + (((slot-1) + (pin-1)) % 4);
|
||||
case 4:
|
||||
return LASAT_IRQ_ETH1; /* Ethernet 1 (LAN 2) */
|
||||
case 5:
|
||||
return LASAT_IRQ_ETH0; /* Ethernet 0 (LAN 1) */
|
||||
case 6:
|
||||
return LASAT_IRQ_HDC; /* IDE controller */
|
||||
default:
|
||||
return 0xff; /* Illegal */
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Do platform specific device initialization at pci_enable_device() time */
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user