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Merge branch 'spi-5.3' into spi-next

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This commit is contained in:
Mark Brown
2019-07-04 17:35:07 +01:00
parent 2337ff4529 8cc7720470
commit 106dbe24d4
33 changed files with 2284 additions and 541 deletions
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20
Documentation/devicetree/bindings/mfd/atmel-usart.txt
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@@ -17,17 +17,24 @@ Required properties for USART in SPI mode:
- cs-gpios: chipselects (internal cs not supported)
- atmel,usart-mode : Must be <AT91_USART_MODE_SPI> (found in dt-bindings/mfd/at91-usart.h)
Optional properties in serial and SPI mode:
- dma bindings for dma transfer:
- dmas: DMA specifier, consisting of a phandle to DMA controller node,
memory peripheral interface and USART DMA channel ID, FIFO configuration.
The order of DMA channels is fixed. The first DMA channel must be TX
associated channel and the second one must be RX associated channel.
Refer to dma.txt and atmel-dma.txt for details.
- dma-names: "tx" for TX channel.
"rx" for RX channel.
The order of dma-names is also fixed. The first name must be "tx"
and the second one must be "rx" as in the examples below.
Optional properties in serial mode:
- atmel,use-dma-rx: use of PDC or DMA for receiving data
- atmel,use-dma-tx: use of PDC or DMA for transmitting data
- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively.
It will use specified PIO instead of the peripheral function pin for the USART feature.
If unsure, don't specify this property.
- add dma bindings for dma transfer:
- dmas: DMA specifier, consisting of a phandle to DMA controller node,
memory peripheral interface and USART DMA channel ID, FIFO configuration.
Refer to dma.txt and atmel-dma.txt for details.
- dma-names: "rx" for RX channel, "tx" for TX channel.
- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
capable USARTs.
- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt
@@ -81,5 +88,8 @@ Example:
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
clocks = <&usart0_clk>;
clock-names = "usart";
dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
<&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
cs-gpios = <&pioB 3 0>;
};

86
Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml Normal file
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@@ -0,0 +1,86 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/allwinner,sun4i-a10-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 SPI Controller Device Tree Bindings
allOf:
- $ref: "spi-controller.yaml"
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
"#address-cells": true
"#size-cells": true
compatible:
const: allwinner,sun4i-a10-spi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
clock-names:
items:
- const: ahb
- const: mod
dmas:
items:
- description: RX DMA Channel
- description: TX DMA Channel
dma-names:
items:
- const: rx
- const: tx
num-cs: true
patternProperties:
"^.*@[0-9a-f]+":
properties:
reg:
items:
minimum: 0
maximum: 4
spi-rx-bus-width:
const: 1
spi-tx-bus-width:
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
spi1: spi@1c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
clocks = <&ahb_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
#address-cells = <1>;
#size-cells = <0>;
};
...

106
Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml Normal file
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@@ -0,0 +1,106 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/allwinner,sun6i-a31-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A31 SPI Controller Device Tree Bindings
allOf:
- $ref: "spi-controller.yaml"
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
"#address-cells": true
"#size-cells": true
compatible:
enum:
- allwinner,sun6i-a31-spi
- allwinner,sun8i-h3-spi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
clock-names:
items:
- const: ahb
- const: mod
resets:
maxItems: 1
dmas:
items:
- description: RX DMA Channel
- description: TX DMA Channel
dma-names:
items:
- const: rx
- const: tx
num-cs: true
patternProperties:
"^.*@[0-9a-f]+":
properties:
reg:
items:
minimum: 0
maximum: 4
spi-rx-bus-width:
const: 1
spi-tx-bus-width:
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
spi1: spi@1c69000 {
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c69000 0x1000>;
interrupts = <0 66 4>;
clocks = <&ahb1_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
resets = <&ahb1_rst 21>;
#address-cells = <1>;
#size-cells = <0>;
};
- |
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
interrupts = <0 65 4>;
clocks = <&ccu 30>, <&ccu 82>;
clock-names = "ahb", "mod";
dmas = <&dma 23>, <&dma 23>;
dma-names = "rx", "tx";
resets = <&ccu 15>;
#address-cells = <1>;
#size-cells = <0>;
};
...

112
Documentation/devicetree/bindings/spi/spi-bus.txt
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@@ -1,111 +1 @@
SPI (Serial Peripheral Interface) busses
SPI busses can be described with a node for the SPI controller device
and a set of child nodes for each SPI slave on the bus. The system's SPI
controller may be described for use in SPI master mode or in SPI slave mode,
but not for both at the same time.
The SPI controller node requires the following properties:
- compatible - Name of SPI bus controller following generic names
recommended practice.
In master mode, the SPI controller node requires the following additional
properties:
- #address-cells - number of cells required to define a chip select
address on the SPI bus.
- #size-cells - should be zero.
In slave mode, the SPI controller node requires one additional property:
- spi-slave - Empty property.
No other properties are required in the SPI bus node. It is assumed
that a driver for an SPI bus device will understand that it is an SPI bus.
However, the binding does not attempt to define the specific method for
assigning chip select numbers. Since SPI chip select configuration is
flexible and non-standardized, it is left out of this binding with the
assumption that board specific platform code will be used to manage
chip selects. Individual drivers can define additional properties to
support describing the chip select layout.
Optional properties (master mode only):
- cs-gpios - gpios chip select.
- num-cs - total number of chipselects.
If cs-gpios is used the number of chip selects will be increased automatically
with max(cs-gpios > hw cs).
So if for example the controller has 2 CS lines, and the cs-gpios
property looks like this:
cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
Then it should be configured so that num_chipselect = 4 with the
following mapping:
cs0 : &gpio1 0 0
cs1 : native
cs2 : &gpio1 1 0
cs3 : &gpio1 2 0
SPI slave nodes must be children of the SPI controller node.
In master mode, one or more slave nodes (up to the number of chip selects) can
be present. Required properties are:
- compatible - Name of SPI device following generic names recommended
practice.
- reg - Chip select address of device.
- spi-max-frequency - Maximum SPI clocking speed of device in Hz.
In slave mode, the (single) slave node is optional.
If present, it must be called "slave". Required properties are:
- compatible - Name of SPI device following generic names recommended
practice.
All slave nodes can contain the following optional properties:
- spi-cpol - Empty property indicating device requires inverse clock
polarity (CPOL) mode.
- spi-cpha - Empty property indicating device requires shifted clock
phase (CPHA) mode.
- spi-cs-high - Empty property indicating device requires chip select
active high.
- spi-3wire - Empty property indicating device requires 3-wire mode.
- spi-lsb-first - Empty property indicating device requires LSB first mode.
- spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI.
Defaults to 1 if not present.
- spi-rx-bus-width - The bus width (number of data wires) that is used for MISO.
Defaults to 1 if not present.
- spi-rx-delay-us - Microsecond delay after a read transfer.
- spi-tx-delay-us - Microsecond delay after a write transfer.
Some SPI controllers and devices support Dual and Quad SPI transfer mode.
It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4
wires (QUAD).
Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
only 1 (SINGLE), 2 (DUAL) and 4 (QUAD).
Dual/Quad mode is not allowed when 3-wire mode is used.
If a gpio chipselect is used for the SPI slave the gpio number will be passed
via the SPI master node cs-gpios property.
SPI example for an MPC5200 SPI bus:
spi@f00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
ethernet-switch@0 {
compatible = "micrel,ks8995m";
spi-max-frequency = <1000000>;
reg = <0>;
};
codec@1 {
compatible = "ti,tlv320aic26";
spi-max-frequency = <100000>;
reg = <1>;
};
};
This file has moved to spi-controller.yaml.

161
Documentation/devicetree/bindings/spi/spi-controller.yaml Normal file
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@@ -0,0 +1,161 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SPI Controller Generic Binding
maintainers:
- Mark Brown <broonie@kernel.org>
description: |
SPI busses can be described with a node for the SPI controller device
and a set of child nodes for each SPI slave on the bus. The system SPI
controller may be described for use in SPI master mode or in SPI slave mode,
but not for both at the same time.
properties:
$nodename:
pattern: "^spi(@.*|-[0-9a-f])*$"
"#address-cells":
const: 1
"#size-cells":
const: 0
cs-gpios:
description: |
GPIOs used as chip selects.
If that property is used, the number of chip selects will be
increased automatically with max(cs-gpios, hardware chip selects).
So if, for example, the controller has 2 CS lines, and the
cs-gpios looks like this
cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
Then it should be configured so that num_chipselect = 4, with
the following mapping
cs0 : &gpio1 0 0
cs1 : native
cs2 : &gpio1 1 0
cs3 : &gpio1 2 0
num-cs:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Total number of chip selects.
spi-slave:
$ref: /schemas/types.yaml#/definitions/flag
description:
The SPI controller acts as a slave, instead of a master.
patternProperties:
"^slave$":
type: object
properties:
compatible:
description:
Compatible of the SPI device.
required:
- compatible
"^.*@[0-9a-f]+$":
type: object
properties:
compatible:
description:
Compatible of the SPI device.
reg:
maxItems: 1
minimum: 0
maximum: 256
description:
Chip select used by the device.
spi-3wire:
$ref: /schemas/types.yaml#/definitions/flag
description:
The device requires 3-wire mode.
spi-cpha:
$ref: /schemas/types.yaml#/definitions/flag
description:
The device requires shifted clock phase (CPHA) mode.
spi-cpol:
$ref: /schemas/types.yaml#/definitions/flag
description:
The device requires inverse clock polarity (CPOL) mode.
spi-cs-high:
$ref: /schemas/types.yaml#/definitions/flag
description:
The device requires the chip select active high.
spi-lsb-first:
$ref: /schemas/types.yaml#/definitions/flag
description:
The device requires the LSB first mode.
spi-max-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Maximum SPI clocking speed of the device in Hz.
spi-rx-bus-width:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 1, 2, 4 ]
- default: 1
description:
Bus width to the SPI bus used for MISO.
spi-rx-delay-us:
description:
Delay, in microseconds, after a read transfer.
spi-tx-bus-width:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 1, 2, 4 ]
- default: 1
description:
Bus width to the SPI bus used for MOSI.
spi-tx-delay-us:
description:
Delay, in microseconds, after a write transfer.
required:
- compatible
- reg
examples:
- |
spi@f00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
ethernet-switch@0 {
compatible = "micrel,ks8995m";
spi-max-frequency = <1000000>;
reg = <0>;
};
codec@1 {
compatible = "ti,tlv320aic26";
spi-max-frequency = <100000>;
reg = <1>;
};
};

43
Documentation/devicetree/bindings/spi/spi-gpio.txt
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@@ -1,43 +0,0 @@
SPI-GPIO devicetree bindings
This represents a group of 3-n GPIO lines used for bit-banged SPI on dedicated
GPIO lines.
Required properties:
- compatible: should be set to "spi-gpio"
- #address-cells: should be set to <0x1>
- ranges
- sck-gpios: GPIO spec for the SCK line to use
- miso-gpios: GPIO spec for the MISO line to use
- mosi-gpios: GPIO spec for the MOSI line to use
- cs-gpios: GPIOs to use for chipselect lines.
Not needed if num-chipselects = <0>.
- num-chipselects: Number of chipselect lines. Should be <0> if a single device
with no chip select is connected.
Deprecated bindings:
These legacy GPIO line bindings can alternatively be used to define the
GPIO lines used, they should not be used in new device trees.
- gpio-sck: GPIO spec for the SCK line to use
- gpio-miso: GPIO spec for the MISO line to use
- gpio-mosi: GPIO spec for the MOSI line to use
Example:
spi {
compatible = "spi-gpio";
#address-cells = <0x1>;
ranges;
sck-gpios = <&gpio 95 0>;
miso-gpios = <&gpio 98 0>;
mosi-gpios = <&gpio 97 0>;
cs-gpios = <&gpio 125 0>;
num-chipselects = <1>;
/* clients */
};

72
Documentation/devicetree/bindings/spi/spi-gpio.yaml Normal file
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@@ -0,0 +1,72 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SPI-GPIO devicetree bindings
maintainers:
- Rob Herring <robh@kernel.org>
description:
This represents a group of 3-n GPIO lines used for bit-banged SPI on
dedicated GPIO lines.
allOf:
- $ref: "/schemas/spi/spi-controller.yaml#"
properties:
compatible:
const: spi-gpio
sck-gpios:
description: GPIO spec for the SCK line to use
maxItems: 1
miso-gpios:
description: GPIO spec for the MISO line to use
maxItems: 1
mosi-gpios:
description: GPIO spec for the MOSI line to use
maxItems: 1
cs-gpios:
description: GPIOs to use for chipselect lines.
Not needed if num-chipselects = <0>.
minItems: 1
maxItems: 1024
num-chipselects:
description: Number of chipselect lines. Should be <0> if a single device
with no chip select is connected.
$ref: "/schemas/types.yaml#/definitions/uint32"
# Deprecated properties
gpio-sck: false
gpio-miso: false
gpio-mosi: false
required:
- compatible
- num-chipselects
- sck-gpios
examples:
- |
spi {
compatible = "spi-gpio";
#address-cells = <0x1>;
#size-cells = <0x0>;
sck-gpios = <&gpio 95 0>;
miso-gpios = <&gpio 98 0>;
mosi-gpios = <&gpio 97 0>;
cs-gpios = <&gpio 125 0>;
num-chipselects = <1>;
/* clients */
};
...

165
Documentation/devicetree/bindings/spi/spi-pl022.yaml Normal file
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@@ -0,0 +1,165 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-pl022.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM PL022 SPI controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
allOf:
- $ref: "spi-controller.yaml#"
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
const: arm,pl022
required:
- compatible
properties:
compatible:
items:
- const: arm,pl022
- const: arm,primecell
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- enum:
- SSPCLK
- sspclk
- const: apb_pclk
pl022,autosuspend-delay:
description: delay in ms following transfer completion before the
runtime power management system suspends the device. A setting of 0
indicates no delay and the device will be suspended immediately.
$ref: "/schemas/types.yaml#/definitions/uint32"
pl022,rt:
description: indicates the controller should run the message pump with realtime
priority to minimise the transfer latency on the bus (boolean)
type: boolean
dmas:
description:
Two or more DMA channel specifiers following the convention outlined
in bindings/dma/dma.txt
minItems: 2
maxItems: 32
dma-names:
description:
There must be at least one channel named "tx" for transmit and named "rx"
for receive.
minItems: 2
maxItems: 32
additionalItems: true
items:
- const: rx
- const: tx
patternProperties:
"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
type: object
# SPI slave nodes must be children of the SPI master node and can
# contain the following properties.
properties:
pl022,interface:
description: SPI interface type
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- enum:
- 0 # SPI
- 1 # Texas Instruments Synchronous Serial Frame Format
- 2 # Microwire (Half Duplex)
pl022,com-mode:
description: Specifies the transfer mode
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- enum:
- 0 # interrupt mode
- 1 # polling mode
- 2 # DMA mode
default: 1
pl022,rx-level-trig:
description: Rx FIFO watermark level
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
maximum: 4
pl022,tx-level-trig:
description: Tx FIFO watermark level
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
maximum: 4
pl022,ctrl-len:
description: Microwire interface - Control length
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0x03
maximum: 0x1f
pl022,wait-state:
description: Microwire interface - Wait state
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- enum: [ 0, 1 ]
pl022,duplex:
description: Microwire interface - Full/Half duplex
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- enum: [ 0, 1 ]
required:
- compatible
- reg
- interrupts
examples:
- |
spi@e0100000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xe0100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 31 0x4>;
dmas = <&dma_controller 23 1>,
<&dma_controller 24 0>;
dma-names = "rx", "tx";
m25p80@1 {
compatible = "st,m25p80";
reg = <1>;
spi-max-frequency = <12000000>;
spi-cpol;
spi-cpha;
pl022,interface = <0>;
pl022,com-mode = <0x2>;
pl022,rx-level-trig = <0>;
pl022,tx-level-trig = <0>;
pl022,ctrl-len = <0x11>;
pl022,wait-state = <0>;
pl022,duplex = <0>;
};
};
...

5
Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt
View File

@@ -19,8 +19,11 @@ Required properties:
- reg: chip-Select number (QSPI controller may connect 2 flashes)
- spi-max-frequency: max frequency of spi bus
Optional property:
Optional properties:
- spi-rx-bus-width: see ./spi-bus.txt for the description
- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
Documentation/devicetree/bindings/dma/dma.txt.
- dma-names: DMA request names should include "tx" and "rx" if present.
Example:

23
Documentation/devicetree/bindings/spi/spi-sun4i.txt
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@@ -1,23 +0,0 @@
Allwinner A10 SPI controller
Required properties:
- compatible: Should be "allwinner,sun4-a10-spi".
- reg: Should contain register location and length.
- interrupts: Should contain interrupt.
- clocks: phandle to the clocks feeding the SPI controller. Two are
needed:
- "ahb": the gated AHB parent clock
- "mod": the parent module clock
- clock-names: Must contain the clock names described just above
Example:
spi1: spi@1c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
clocks = <&ahb_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
#address-cells = <1>;
#size-cells = <0>;
};

44
Documentation/devicetree/bindings/spi/spi-sun6i.txt
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@@ -1,44 +0,0 @@
Allwinner A31/H3 SPI controller
Required properties:
- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi".
- reg: Should contain register location and length.
- interrupts: Should contain interrupt.
- clocks: phandle to the clocks feeding the SPI controller. Two are
needed:
- "ahb": the gated AHB parent clock
- "mod": the parent module clock
- clock-names: Must contain the clock names described just above
- resets: phandle to the reset controller asserting this device in
reset
Optional properties:
- dmas: DMA specifiers for rx and tx dma. See the DMA client binding,
Documentation/devicetree/bindings/dma/dma.txt
- dma-names: DMA request names should include "rx" and "tx" if present.
Example:
spi1: spi@1c69000 {
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c69000 0x1000>;
interrupts = <0 66 4>;
clocks = <&ahb1_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
resets = <&ahb1_rst 21>;
};
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
dmas = <&dma 23>, <&dma 23>;
dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
resets = <&ccu RST_BUS_SPI0>;
#address-cells = <1>;
#size-cells = <0>;
};

27
Documentation/devicetree/bindings/spi/spi-synquacer.txt Normal file
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* Socionext Synquacer HS-SPI bindings
Required Properties:
- compatible: should be "socionext,synquacer-spi"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: should contain the "spi_rx", "spi_tx" and "spi_fault" interrupts.
- clocks: core clock iHCLK. Optional rate clock iPCLK (default is iHCLK)
- clock-names: Shall be "iHCLK" and "iPCLK" respectively
Optional Properties:
- socionext,use-rtm: boolean, if required to use "retimed clock" for RX
- socionext,set-aces: boolean, if same active clock edges field to be set.
Example:
spi0: spi@ff110000 {
compatible = "socionext,synquacer-spi";
reg = <0xff110000 0x1000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hsspi>;
clock-names = "iHCLK";
socionext,use-rtm;
socionext,set-aces;
};

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Documentation/devicetree/bindings/spi/spi_pl022.txt
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ARM PL022 SPI controller
Required properties:
- compatible : "arm,pl022", "arm,primecell"
- reg : Offset and length of the register set for the device
- interrupts : Should contain SPI controller interrupt
- num-cs : total number of chipselects
Optional properties:
- cs-gpios : should specify GPIOs used for chipselects.
The gpios will be referred to as reg = <index> in the SPI child nodes.
If unspecified, a single SPI device without a chip select can be used.
- pl022,autosuspend-delay : delay in ms following transfer completion before
the runtime power management system suspends the
device. A setting of 0 indicates no delay and the
device will be suspended immediately
- pl022,rt : indicates the controller should run the message pump with realtime
priority to minimise the transfer latency on the bus (boolean)
- dmas : Two or more DMA channel specifiers following the convention outlined
in bindings/dma/dma.txt
- dma-names: Names for the dma channels, if present. There must be at
least one channel named "tx" for transmit and named "rx" for
receive.
SPI slave nodes must be children of the SPI master node and can
contain the following properties.
- pl022,interface : interface type:
0: SPI
1: Texas Instruments Synchronous Serial Frame Format
2: Microwire (Half Duplex)
- pl022,com-mode : specifies the transfer mode:
0: interrupt mode
1: polling mode (default mode if property not present)
2: DMA mode
- pl022,rx-level-trig : Rx FIFO watermark level
- pl022,tx-level-trig : Tx FIFO watermark level
- pl022,ctrl-len : Microwire interface: Control length
- pl022,wait-state : Microwire interface: Wait state
- pl022,duplex : Microwire interface: Full/Half duplex
Example:
spi@e0100000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xe0100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 31 0x4>;
dmas = <&dma-controller 23 1>,
<&dma-controller 24 0>;
dma-names = "rx", "tx";
m25p80@1 {
compatible = "st,m25p80";
reg = <1>;
spi-max-frequency = <12000000>;
spi-cpol;
spi-cpha;
pl022,interface = <0>;
pl022,com-mode = <0x2>;
pl022,rx-level-trig = <0>;
pl022,tx-level-trig = <0>;
pl022,ctrl-len = <0x11>;
pl022,wait-state = <0>;
pl022,duplex = <0>;
};
};