perf_counter: powerpc: Implement generalized cache events for POWER processors
This adds tables of event codes for the generalized cache events for all the currently supported powerpc processors: POWER{4,5,5+,6,7} and PPC970*, plus powerpc-specific code to use these tables when a generalized cache event is requested. Signed-off-by: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <18992.36430.933526.742969@drongo.ozlabs.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Tento commit je obsažen v:
@@ -427,6 +427,46 @@ static int ppc970_generic_events[] = {
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[PERF_COUNT_BRANCH_MISSES] = 0x327, /* PM_GRP_BR_MPRED */
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};
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#define C(x) PERF_COUNT_HW_CACHE_##x
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/*
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* Table of generalized cache-related events.
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* 0 means not supported, -1 means nonsensical, other values
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* are event codes.
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*/
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static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x8810, 0x3810 },
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[C(OP_WRITE)] = { 0x7810, 0x813 },
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[C(OP_PREFETCH)] = { 0x731, 0 },
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},
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[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { 0, 0 },
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},
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[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0 },
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[C(OP_WRITE)] = { 0, 0 },
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[C(OP_PREFETCH)] = { 0x733, 0 },
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},
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[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x704 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x700 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x431, 0x327 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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};
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struct power_pmu ppc970_pmu = {
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.n_counter = 8,
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.max_alternatives = 2,
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@@ -438,4 +478,5 @@ struct power_pmu ppc970_pmu = {
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.disable_pmc = p970_disable_pmc,
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.n_generic = ARRAY_SIZE(ppc970_generic_events),
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.generic_events = ppc970_generic_events,
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.cache_events = &ppc970_cache_events,
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};
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