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ARM: dts: at91: Switch to the new NAND bindings

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Use the new EBI/NAND bindings to declare NAND chips and remove old NAND
nodes along the way.

Note that we keep using old bindings in at91rm9200.dtsi because this
SoC is not supported by the EBI driver.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
This commit is contained in:
Boris Brezillon
2017-05-30 11:20:53 +02:00
committed by Alexandre Belloni
parent d9c41bf30c
commit 1004a2977b
37 changed files with 1289 additions and 953 deletions
Download Patch File Download Diff File Expand all files Collapse all files

88
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@@ -481,6 +481,38 @@
};
};
ebi {
pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
atmel,pins =
<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_ebi_data_8_15: ebi-data-msb-0 {
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_ebi_addr_nand: ebi-addr-0 {
atmel,pins =
<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
@@ -567,34 +599,20 @@
};
nand {
pinctrl_nand: nand-0 {
pinctrl_nand_oe_we: nand-oe-we-0 {
atmel,pins =
<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */
AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */
AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */
AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */
AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */
AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */
AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */
AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */
AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */
AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */
AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */
AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */
AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */
AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */
<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_nand_16bits: nand_16bits-0 {
pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */
AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */
AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */
AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */
AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */
AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */
AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */
AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */
<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
@@ -1213,28 +1231,6 @@
};
};
nand0: nand@40000000 {
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x10000000
0xffffe000 0x600 /* PMECC Registers */
0xffffe600 0x200 /* PMECC Error Location Registers */
0x00108000 0x18000 /* PMECC looup table in ROM code */
>;
atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
atmel,nand-has-dma;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
gpios = <&pioD 5 GPIO_ACTIVE_HIGH
&pioD 4 GPIO_ACTIVE_HIGH
0
>;
status = "disabled";
};
usb0: ohci@00600000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;