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dmaengine: stm32-mdma: remove GISR1 register

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[ Upstream commit 9d6a2d92e450926c483e45eaf426080a19219f4e ]

GISR1 was described in a not up-to-date documentation when the stm32-mdma
driver has been developed. This register has not been added in reference
manual of STM32 SoC with MDMA, which have only 32 MDMA channels.
So remove it from stm32-mdma driver.

Fixes: a4ffb13c89 ("dmaengine: Add STM32 MDMA driver")
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20220504155322.121431-2-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Amelie Delaunay
2022-05-04 17:53:20 +02:00
committed by Greg Kroah-Hartman
parent c1c4405222
commit 0f87bd8b5f
1 changed files with 5 additions and 16 deletions
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13
drivers/dma/stm32-mdma.c
View File

@@ -40,7 +40,6 @@
STM32_MDMA_SHIFT(mask)) STM32_MDMA_SHIFT(mask))
#define STM32_MDMA_GISR0 0x0000 /* MDMA Int Status Reg 1 */ #define STM32_MDMA_GISR0 0x0000 /* MDMA Int Status Reg 1 */
#define STM32_MDMA_GISR1 0x0004 /* MDMA Int Status Reg 2 */
/* MDMA Channel x interrupt/status register */ /* MDMA Channel x interrupt/status register */
#define STM32_MDMA_CISR(x) (0x40 + 0x40 * (x)) /* x = 0..62 */ #define STM32_MDMA_CISR(x) (0x40 + 0x40 * (x)) /* x = 0..62 */
@@ -196,7 +195,7 @@
#define STM32_MDMA_MAX_BUF_LEN 128 #define STM32_MDMA_MAX_BUF_LEN 128
#define STM32_MDMA_MAX_BLOCK_LEN 65536 #define STM32_MDMA_MAX_BLOCK_LEN 65536
#define STM32_MDMA_MAX_CHANNELS 63 #define STM32_MDMA_MAX_CHANNELS 32
#define STM32_MDMA_MAX_REQUESTS 256 #define STM32_MDMA_MAX_REQUESTS 256
#define STM32_MDMA_MAX_BURST 128 #define STM32_MDMA_MAX_BURST 128
#define STM32_MDMA_VERY_HIGH_PRIORITY 0x11 #define STM32_MDMA_VERY_HIGH_PRIORITY 0x11
@@ -1350,21 +1349,11 @@ static irqreturn_t stm32_mdma_irq_handler(int irq, void *devid)
/* Find out which channel generates the interrupt */ /* Find out which channel generates the interrupt */
status = readl_relaxed(dmadev->base + STM32_MDMA_GISR0); status = readl_relaxed(dmadev->base + STM32_MDMA_GISR0);
if (status) {
id = __ffs(status);
} else {
status = readl_relaxed(dmadev->base + STM32_MDMA_GISR1);
if (!status) { if (!status) {
dev_dbg(mdma2dev(dmadev), "spurious it\n"); dev_dbg(mdma2dev(dmadev), "spurious it\n");
return IRQ_NONE; return IRQ_NONE;
} }
id = __ffs(status); id = __ffs(status);
/*
* As GISR0 provides status for channel id from 0 to 31,
* so GISR1 provides status for channel id from 32 to 62
*/
id += 32;
}
chan = &dmadev->chan[id]; chan = &dmadev->chan[id];
if (!chan) { if (!chan) {