ARM: msm: irq_data conversion.
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca> Acked-by: Gregory Bean <gbean@codeaurora.org> Acked-by: Daniel Walker <dwalker@codeaurora.org>
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@@ -42,12 +42,11 @@ static struct sirc_cascade_regs sirc_reg_table[] = {
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/* Mask off the given interrupt. Keep the int_enable mask in sync with
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the enable reg, so it can be restored after power collapse. */
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static void sirc_irq_mask(unsigned int irq)
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static void sirc_irq_mask(struct irq_data *d)
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{
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unsigned int mask;
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mask = 1 << (irq - FIRST_SIRC_IRQ);
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mask = 1 << (d->irq - FIRST_SIRC_IRQ);
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writel(mask, sirc_regs.int_enable_clear);
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int_enable &= ~mask;
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return;
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@@ -55,31 +54,31 @@ static void sirc_irq_mask(unsigned int irq)
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/* Unmask the given interrupt. Keep the int_enable mask in sync with
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the enable reg, so it can be restored after power collapse. */
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static void sirc_irq_unmask(unsigned int irq)
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static void sirc_irq_unmask(struct irq_data *d)
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{
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unsigned int mask;
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mask = 1 << (irq - FIRST_SIRC_IRQ);
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mask = 1 << (d->irq - FIRST_SIRC_IRQ);
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writel(mask, sirc_regs.int_enable_set);
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int_enable |= mask;
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return;
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}
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static void sirc_irq_ack(unsigned int irq)
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static void sirc_irq_ack(struct irq_data *d)
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{
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unsigned int mask;
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mask = 1 << (irq - FIRST_SIRC_IRQ);
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mask = 1 << (d->irq - FIRST_SIRC_IRQ);
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writel(mask, sirc_regs.int_clear);
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return;
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}
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static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
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static int sirc_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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unsigned int mask;
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/* Used to set the interrupt enable mask during power collapse. */
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mask = 1 << (irq - FIRST_SIRC_IRQ);
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mask = 1 << (d->irq - FIRST_SIRC_IRQ);
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if (on)
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wake_enable |= mask;
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else
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@@ -88,12 +87,12 @@ static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
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return 0;
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}
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static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
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static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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unsigned int mask;
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unsigned int val;
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mask = 1 << (irq - FIRST_SIRC_IRQ);
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mask = 1 << (d->irq - FIRST_SIRC_IRQ);
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val = readl(sirc_regs.int_polarity);
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if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
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@@ -106,10 +105,10 @@ static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
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val = readl(sirc_regs.int_type);
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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val |= mask;
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irq_desc[irq].handle_irq = handle_edge_irq;
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irq_desc[d->irq].handle_irq = handle_edge_irq;
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} else {
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val &= ~mask;
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irq_desc[irq].handle_irq = handle_level_irq;
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irq_desc[d->irq].handle_irq = handle_level_irq;
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}
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writel(val, sirc_regs.int_type);
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@@ -139,16 +138,16 @@ static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
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;
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generic_handle_irq(sirq+FIRST_SIRC_IRQ);
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desc->chip->ack(irq);
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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}
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static struct irq_chip sirc_irq_chip = {
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.name = "sirc",
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.ack = sirc_irq_ack,
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.mask = sirc_irq_mask,
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.unmask = sirc_irq_unmask,
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.set_wake = sirc_irq_set_wake,
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.set_type = sirc_irq_set_type,
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.name = "sirc",
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.irq_ack = sirc_irq_ack,
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.irq_mask = sirc_irq_mask,
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.irq_unmask = sirc_irq_unmask,
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.irq_set_wake = sirc_irq_set_wake,
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.irq_set_type = sirc_irq_set_type,
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};
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void __init msm_init_sirc(void)
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