MIPS: MSP71xx: Move code.
Now that Yosemite's gone we can move the MSP71xx code one level up. Shane McDonald <mcdonald.shane@gmail.com>'s https://patchwork.linux-mips.org/patch/4736/ has been folded into this patch. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
216
arch/mips/pmcs-msp71xx/msp_irq_cic.c
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216
arch/mips/pmcs-msp71xx/msp_irq_cic.c
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/*
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* Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c
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*
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* This file define the irq handler for MSP CIC subsystem interrupts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <asm/mipsregs.h>
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#include <msp_cic_int.h>
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#include <msp_regs.h>
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/*
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* External API
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*/
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extern void msp_per_irq_init(void);
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extern void msp_per_irq_dispatch(void);
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/*
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* Convenience Macro. Should be somewhere generic.
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*/
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#define get_current_vpe() \
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((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
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#ifdef CONFIG_SMP
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#define LOCK_VPE(flags, mtflags) \
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do { \
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local_irq_save(flags); \
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mtflags = dmt(); \
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} while (0)
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#define UNLOCK_VPE(flags, mtflags) \
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do { \
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emt(mtflags); \
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local_irq_restore(flags);\
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} while (0)
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#define LOCK_CORE(flags, mtflags) \
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do { \
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local_irq_save(flags); \
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mtflags = dvpe(); \
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} while (0)
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#define UNLOCK_CORE(flags, mtflags) \
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do { \
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evpe(mtflags); \
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local_irq_restore(flags);\
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} while (0)
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#else
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#define LOCK_VPE(flags, mtflags)
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#define UNLOCK_VPE(flags, mtflags)
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#endif
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/* ensure writes to cic are completed */
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static inline void cic_wmb(void)
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{
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const volatile void __iomem *cic_mem = CIC_VPE0_MSK_REG;
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volatile u32 dummy_read;
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wmb();
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dummy_read = __raw_readl(cic_mem);
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dummy_read++;
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}
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static void unmask_cic_irq(struct irq_data *d)
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{
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volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG;
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int vpe;
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#ifdef CONFIG_SMP
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unsigned int mtflags;
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unsigned long flags;
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/*
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* Make sure we have IRQ affinity. It may have changed while
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* we were processing the IRQ.
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*/
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if (!cpumask_test_cpu(smp_processor_id(), d->affinity))
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return;
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#endif
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vpe = get_current_vpe();
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LOCK_VPE(flags, mtflags);
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cic_msk_reg[vpe] |= (1 << (d->irq - MSP_CIC_INTBASE));
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UNLOCK_VPE(flags, mtflags);
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cic_wmb();
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}
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static void mask_cic_irq(struct irq_data *d)
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{
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volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG;
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int vpe = get_current_vpe();
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#ifdef CONFIG_SMP
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unsigned long flags, mtflags;
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#endif
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LOCK_VPE(flags, mtflags);
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cic_msk_reg[vpe] &= ~(1 << (d->irq - MSP_CIC_INTBASE));
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UNLOCK_VPE(flags, mtflags);
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cic_wmb();
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}
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static void msp_cic_irq_ack(struct irq_data *d)
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{
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mask_cic_irq(d);
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/*
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* Only really necessary for 18, 16-14 and sometimes 3:0
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* (since these can be edge sensitive) but it doesn't
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* hurt for the others
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*/
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*CIC_STS_REG = (1 << (d->irq - MSP_CIC_INTBASE));
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smtc_im_ack_irq(d->irq);
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}
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/*Note: Limiting to VSMP . Not tested in SMTC */
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#ifdef CONFIG_MIPS_MT_SMP
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static int msp_cic_irq_set_affinity(struct irq_data *d,
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const struct cpumask *cpumask, bool force)
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{
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int cpu;
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unsigned long flags;
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unsigned int mtflags;
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unsigned long imask = (1 << (irq - MSP_CIC_INTBASE));
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volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG;
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/* timer balancing should be disabled in kernel code */
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BUG_ON(irq == MSP_INT_VPE0_TIMER || irq == MSP_INT_VPE1_TIMER);
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LOCK_CORE(flags, mtflags);
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/* enable if any of each VPE's TCs require this IRQ */
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for_each_online_cpu(cpu) {
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if (cpumask_test_cpu(cpu, cpumask))
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cic_mask[cpu] |= imask;
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else
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cic_mask[cpu] &= ~imask;
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}
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UNLOCK_CORE(flags, mtflags);
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return 0;
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}
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#endif
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static struct irq_chip msp_cic_irq_controller = {
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.name = "MSP_CIC",
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.irq_mask = mask_cic_irq,
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.irq_mask_ack = msp_cic_irq_ack,
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.irq_unmask = unmask_cic_irq,
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.irq_ack = msp_cic_irq_ack,
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#ifdef CONFIG_MIPS_MT_SMP
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.irq_set_affinity = msp_cic_irq_set_affinity,
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#endif
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};
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void __init msp_cic_irq_init(void)
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{
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int i;
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/* Mask/clear interrupts. */
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*CIC_VPE0_MSK_REG = 0x00000000;
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*CIC_VPE1_MSK_REG = 0x00000000;
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*CIC_STS_REG = 0xFFFFFFFF;
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/*
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* The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
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* These inputs map to EXT_INT_POL[6:4] inside the CIC.
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* They are to be active low, level sensitive.
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*/
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*CIC_EXT_CFG_REG &= 0xFFFF8F8F;
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/* initialize all the IRQ descriptors */
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for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) {
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irq_set_chip_and_handler(i, &msp_cic_irq_controller,
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handle_level_irq);
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#ifdef CONFIG_MIPS_MT_SMTC
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/* Mask of CIC interrupt */
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irq_hwmask[i] = C_IRQ4;
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#endif
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}
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/* Initialize the PER interrupt sub-system */
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msp_per_irq_init();
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}
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/* CIC masked by CIC vector processing before dispatch called */
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void msp_cic_irq_dispatch(void)
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{
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volatile u32 *cic_msk_reg = (volatile u32 *)CIC_VPE0_MSK_REG;
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u32 cic_mask;
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u32 pending;
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int cic_status = *CIC_STS_REG;
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cic_mask = cic_msk_reg[get_current_vpe()];
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pending = cic_status & cic_mask;
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if (pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))) {
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do_IRQ(MSP_INT_VPE0_TIMER);
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} else if (pending & (1 << (MSP_INT_VPE1_TIMER - MSP_CIC_INTBASE))) {
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do_IRQ(MSP_INT_VPE1_TIMER);
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} else if (pending & (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) {
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msp_per_irq_dispatch();
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} else if (pending) {
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do_IRQ(ffs(pending) + MSP_CIC_INTBASE - 1);
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} else{
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spurious_interrupt();
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}
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}
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