xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'drm/drm-next' into drm-misc-next

Browse Source 
drm-next is forwarded to v4.20-rc1, and we need this to make
a patch series apply.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
This commit is contained in:
Maarten Lankhorst
2018-11-13 10:58:49 +01:00
parent 913240696e 651022382c
commit 0ea0397a3a
10025 changed files with 504995 additions and 228244 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
include/acpi/acconfig.h
View File

@@ -173,11 +173,20 @@
#define ACPI_RSDP_CHECKSUM_LENGTH 20
#define ACPI_RSDP_XCHECKSUM_LENGTH 36
/* SMBus, GSBus and IPMI bidirectional buffer size */
/*
* SMBus, GSBus and IPMI buffer sizes. All have a 2-byte header,
* containing both Status and Length.
*/
#define ACPI_SERIAL_HEADER_SIZE 2 /* Common for below. Status and Length fields */
#define ACPI_SMBUS_BUFFER_SIZE 34
#define ACPI_GSBUS_BUFFER_SIZE 34
#define ACPI_IPMI_BUFFER_SIZE 66
#define ACPI_SMBUS_DATA_SIZE 32
#define ACPI_SMBUS_BUFFER_SIZE ACPI_SERIAL_HEADER_SIZE + ACPI_SMBUS_DATA_SIZE
#define ACPI_IPMI_DATA_SIZE 64
#define ACPI_IPMI_BUFFER_SIZE ACPI_SERIAL_HEADER_SIZE + ACPI_IPMI_DATA_SIZE
#define ACPI_MAX_GSBUS_DATA_SIZE 255
#define ACPI_MAX_GSBUS_BUFFER_SIZE ACPI_SERIAL_HEADER_SIZE + ACPI_MAX_GSBUS_DATA_SIZE
/* _sx_d and _sx_w control methods */

9
include/acpi/acexcep.h
View File

@@ -171,8 +171,10 @@ struct acpi_exception_info {
#define AE_AML_LOOP_TIMEOUT EXCEP_AML (0x0021)
#define AE_AML_UNINITIALIZED_NODE EXCEP_AML (0x0022)
#define AE_AML_TARGET_TYPE EXCEP_AML (0x0023)
#define AE_AML_PROTOCOL EXCEP_AML (0x0024)
#define AE_AML_BUFFER_LENGTH EXCEP_AML (0x0025)
#define AE_CODE_AML_MAX 0x0023
#define AE_CODE_AML_MAX 0x0025
/*
* Internal exceptions used for control
@@ -347,7 +349,10 @@ static const struct acpi_exception_info acpi_gbl_exception_names_aml[] = {
EXCEP_TXT("AE_AML_UNINITIALIZED_NODE",
"A namespace node is uninitialized or unresolved"),
EXCEP_TXT("AE_AML_TARGET_TYPE",
"A target operand of an incorrect type was encountered")
"A target operand of an incorrect type was encountered"),
EXCEP_TXT("AE_AML_PROTOCOL", "Violation of a fixed ACPI protocol"),
EXCEP_TXT("AE_AML_BUFFER_LENGTH",
"The length of the buffer is invalid/incorrect")
};
static const struct acpi_exception_info acpi_gbl_exception_names_ctrl[] = {

9
include/acpi/acpi_bus.h
View File

@@ -346,10 +346,16 @@ struct acpi_device_physical_node {
bool put_online:1;
};
struct acpi_device_properties {
const guid_t *guid;
const union acpi_object *properties;
struct list_head list;
};
/* ACPI Device Specific Data (_DSD) */
struct acpi_device_data {
const union acpi_object *pointer;
const union acpi_object *properties;
struct list_head properties;
const union acpi_object *of_compatible;
struct list_head subnodes;
};
@@ -595,7 +601,6 @@ enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev);
int acpi_dma_get_range(struct device *dev, u64 *dma_addr, u64 *offset,
u64 *size);
int acpi_dma_configure(struct device *dev, enum dev_dma_attr attr);
void acpi_dma_deconfigure(struct device *dev);
struct acpi_device *acpi_find_child_device(struct acpi_device *parent,
u64 address, bool check_children);

9
include/acpi/acpixf.h
View File

@@ -12,7 +12,7 @@
/* Current ACPICA subsystem version in YYYYMMDD format */
#define ACPI_CA_VERSION 0x20180810
#define ACPI_CA_VERSION 0x20181003
#include <acpi/acconfig.h>
#include <acpi/actypes.h>
@@ -156,13 +156,6 @@ ACPI_INIT_GLOBAL(u8, acpi_gbl_copy_dsdt_locally, FALSE);
*/
ACPI_INIT_GLOBAL(u8, acpi_gbl_do_not_use_xsdt, FALSE);
/*
* Optionally support group module level code.
* NOTE, this is essentially obsolete and will be removed soon
* (01/2018).
*/
ACPI_INIT_GLOBAL(u8, acpi_gbl_group_module_level_code, FALSE);
/*
* Optionally support module level code by parsing an entire table as
* a method as it is loaded. Default is TRUE.

1
include/acpi/cppc_acpi.h
View File

@@ -104,6 +104,7 @@ enum cppc_regs {
* today.
*/
struct cppc_perf_caps {
u32 guaranteed_perf;
u32 highest_perf;
u32 nominal_perf;
u32 lowest_perf;

8
include/asm-generic/bug.h
View File

@@ -17,10 +17,8 @@
#ifndef __ASSEMBLY__
#include <linux/kernel.h>
#ifdef CONFIG_BUG
#ifdef CONFIG_GENERIC_BUG
struct bug_entry {
#ifdef CONFIG_GENERIC_BUG
#ifndef CONFIG_GENERIC_BUG_RELATIVE_POINTERS
unsigned long bug_addr;
#else
@@ -35,8 +33,10 @@ struct bug_entry {
unsigned short line;
#endif
unsigned short flags;
};
#endif /* CONFIG_GENERIC_BUG */
};
#ifdef CONFIG_BUG
/*
* Don't use BUG() or BUG_ON() unless there's really no way out; one

24
include/asm-generic/compat.h
View File

@@ -1,3 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_GENERIC_COMPAT_H
#define __ASM_GENERIC_COMPAT_H
/* This is an empty stub for 32-bit-only architectures */
/* These types are common across all compat ABIs */
typedef u32 compat_size_t;
typedef s32 compat_ssize_t;
typedef s32 compat_clock_t;
typedef s32 compat_pid_t;
typedef u32 compat_ino_t;
typedef s32 compat_off_t;
typedef s64 compat_loff_t;
typedef s32 compat_daddr_t;
typedef s32 compat_timer_t;
typedef s32 compat_key_t;
typedef s16 compat_short_t;
typedef s32 compat_int_t;
typedef s32 compat_long_t;
typedef u16 compat_ushort_t;
typedef u32 compat_uint_t;
typedef u32 compat_ulong_t;
typedef u32 compat_uptr_t;
typedef u32 compat_aio_context_t;
#endif

9
include/asm-generic/dma-mapping.h
View File

@@ -4,16 +4,7 @@
static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
{
/*
* Use the non-coherent ops if available. If an architecture wants a
* more fine-grained selection of operations it will have to implement
* get_arch_dma_ops itself or use the per-device dma_ops.
*/
#ifdef CONFIG_DMA_NONCOHERENT_OPS
return &dma_noncoherent_ops;
#else
return &dma_direct_ops;
#endif
}
#endif /* _ASM_GENERIC_DMA_MAPPING_H */

88
include/asm-generic/hugetlb.h
View File

@@ -32,7 +32,7 @@ static inline pte_t huge_pte_modify(pte_t pte, pgprot_t newprot)
return pte_modify(pte, newprot);
}
#ifndef huge_pte_clear
#ifndef __HAVE_ARCH_HUGE_PTE_CLEAR
static inline void huge_pte_clear(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long sz)
{
@@ -40,4 +40,90 @@ static inline void huge_pte_clear(struct mm_struct *mm, unsigned long addr,
}
#endif
#ifndef __HAVE_ARCH_HUGETLB_FREE_PGD_RANGE
static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
unsigned long addr, unsigned long end,
unsigned long floor, unsigned long ceiling)
{
free_pgd_range(tlb, addr, end, floor, ceiling);
}
#endif
#ifndef __HAVE_ARCH_HUGE_SET_HUGE_PTE_AT
static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte)
{
set_pte_at(mm, addr, ptep, pte);
}
#endif
#ifndef __HAVE_ARCH_HUGE_PTEP_GET_AND_CLEAR
static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
unsigned long addr, pte_t *ptep)
{
return ptep_get_and_clear(mm, addr, ptep);
}
#endif
#ifndef __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH
static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
ptep_clear_flush(vma, addr, ptep);
}
#endif
#ifndef __HAVE_ARCH_HUGE_PTE_NONE
static inline int huge_pte_none(pte_t pte)
{
return pte_none(pte);
}
#endif
#ifndef __HAVE_ARCH_HUGE_PTE_WRPROTECT
static inline pte_t huge_pte_wrprotect(pte_t pte)
{
return pte_wrprotect(pte);
}
#endif
#ifndef __HAVE_ARCH_PREPARE_HUGEPAGE_RANGE
static inline int prepare_hugepage_range(struct file *file,
unsigned long addr, unsigned long len)
{
struct hstate *h = hstate_file(file);
if (len & ~huge_page_mask(h))
return -EINVAL;
if (addr & ~huge_page_mask(h))
return -EINVAL;
return 0;
}
#endif
#ifndef __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT
static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
unsigned long addr, pte_t *ptep)
{
ptep_set_wrprotect(mm, addr, ptep);
}
#endif
#ifndef __HAVE_ARCH_HUGE_PTEP_SET_ACCESS_FLAGS
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep,
pte_t pte, int dirty)
{
return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
}
#endif
#ifndef __HAVE_ARCH_HUGE_PTEP_GET
static inline pte_t huge_ptep_get(pte_t *ptep)
{
return *ptep;
}
#endif
#endif /* _ASM_GENERIC_HUGETLB_H */

4
include/asm-generic/percpu.h
View File

@@ -62,10 +62,6 @@ extern void setup_per_cpu_areas(void);
#define PER_CPU_ATTRIBUTES
#endif
#ifndef PER_CPU_DEF_ATTRIBUTES
#define PER_CPU_DEF_ATTRIBUTES
#endif
#define raw_cpu_generic_read(pcp) \
({ \
*raw_cpu_ptr(&(pcp)); \

4
include/asm-generic/pgtable.h
View File

@@ -757,7 +757,7 @@ static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
/*
* Interfaces that can be used by architecture code to keep track of
* memory type of pfn mappings specified by the remap_pfn_range,
* vm_insert_pfn.
* vmf_insert_pfn.
*/
/*
@@ -773,7 +773,7 @@ static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
/*
* track_pfn_insert is called when a _new_ single pfn is established
* by vm_insert_pfn().
* by vmf_insert_pfn().
*/
static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
pfn_t pfn)

7
include/asm-generic/qrwlock.h
View File

@@ -71,8 +71,8 @@ static inline int queued_write_trylock(struct qrwlock *lock)
if (unlikely(cnts))
return 0;
return likely(atomic_cmpxchg_acquire(&lock->cnts,
cnts, cnts | _QW_LOCKED) == cnts);
return likely(atomic_try_cmpxchg_acquire(&lock->cnts, &cnts,
_QW_LOCKED));
}
/**
* queued_read_lock - acquire read lock of a queue rwlock
@@ -96,8 +96,9 @@ static inline void queued_read_lock(struct qrwlock *lock)
*/
static inline void queued_write_lock(struct qrwlock *lock)
{
u32 cnts = 0;
/* Optimize for the unfair lock case where the fair flag is 0. */
if (atomic_cmpxchg_acquire(&lock->cnts, 0, _QW_LOCKED) == 0)
if (likely(atomic_try_cmpxchg_acquire(&lock->cnts, &cnts, _QW_LOCKED)))
return;
queued_write_lock_slowpath(lock);

16
include/asm-generic/qspinlock.h
View File

@@ -66,10 +66,12 @@ static __always_inline int queued_spin_is_contended(struct qspinlock *lock)
*/
static __always_inline int queued_spin_trylock(struct qspinlock *lock)
{
if (!atomic_read(&lock->val) &&
(atomic_cmpxchg_acquire(&lock->val, 0, _Q_LOCKED_VAL) == 0))
return 1;
return 0;
u32 val = atomic_read(&lock->val);
if (unlikely(val))
return 0;
return likely(atomic_try_cmpxchg_acquire(&lock->val, &val, _Q_LOCKED_VAL));
}
extern void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
@@ -80,11 +82,11 @@ extern void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
*/
static __always_inline void queued_spin_lock(struct qspinlock *lock)
{
u32 val;
u32 val = 0;
val = atomic_cmpxchg_acquire(&lock->val, 0, _Q_LOCKED_VAL);
if (likely(val == 0))
if (likely(atomic_try_cmpxchg_acquire(&lock->val, &val, _Q_LOCKED_VAL)))
return;
queued_spin_lock_slowpath(lock, val);
}

14
include/asm-generic/sections.h
View File

@@ -141,4 +141,18 @@ static inline bool init_section_intersects(void *virt, size_t size)
return memory_intersects(__init_begin, __init_end, virt, size);
}
/**
* is_kernel_rodata - checks if the pointer address is located in the
* .rodata section
*
* @addr: address to check
*
* Returns: true if the address is located in .rodata, false otherwise.
*/
static inline bool is_kernel_rodata(unsigned long addr)
{
return addr >= (unsigned long)__start_rodata &&
addr < (unsigned long)__end_rodata;
}
#endif /* _ASM_GENERIC_SECTIONS_H_ */

86
include/asm-generic/tlb.h
View File

@@ -20,6 +20,8 @@
#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
#ifdef CONFIG_MMU
#ifdef CONFIG_HAVE_RCU_TABLE_FREE
/*
* Semi RCU freeing of the page directories.
@@ -97,12 +99,30 @@ struct mmu_gather {
#endif
unsigned long start;
unsigned long end;
/* we are in the middle of an operation to clear
* a full mm and can make some optimizations */
unsigned int fullmm : 1,
/* we have performed an operation which
* requires a complete flush of the tlb */
need_flush_all : 1;
/*
* we are in the middle of an operation to clear
* a full mm and can make some optimizations
*/
unsigned int fullmm : 1;
/*
* we have performed an operation which
* requires a complete flush of the tlb
*/
unsigned int need_flush_all : 1;
/*
* we have removed page directories
*/
unsigned int freed_tables : 1;
/*
* at which levels have we cleared entries?
*/
unsigned int cleared_ptes : 1;
unsigned int cleared_pmds : 1;
unsigned int cleared_puds : 1;
unsigned int cleared_p4ds : 1;
struct mmu_gather_batch *active;
struct mmu_gather_batch local;
@@ -118,6 +138,7 @@ void arch_tlb_gather_mmu(struct mmu_gather *tlb,
void tlb_flush_mmu(struct mmu_gather *tlb);
void arch_tlb_finish_mmu(struct mmu_gather *tlb,
unsigned long start, unsigned long end, bool force);
void tlb_flush_mmu_free(struct mmu_gather *tlb);
extern bool __tlb_remove_page_size(struct mmu_gather *tlb, struct page *page,
int page_size);
@@ -137,6 +158,11 @@ static inline void __tlb_reset_range(struct mmu_gather *tlb)
tlb->start = TASK_SIZE;
tlb->end = 0;
}
tlb->freed_tables = 0;
tlb->cleared_ptes = 0;
tlb->cleared_pmds = 0;
tlb->cleared_puds = 0;
tlb->cleared_p4ds = 0;
}
static inline void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb)
@@ -186,6 +212,25 @@ static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb,
}
#endif
static inline unsigned long tlb_get_unmap_shift(struct mmu_gather *tlb)
{
if (tlb->cleared_ptes)
return PAGE_SHIFT;
if (tlb->cleared_pmds)
return PMD_SHIFT;
if (tlb->cleared_puds)
return PUD_SHIFT;
if (tlb->cleared_p4ds)
return P4D_SHIFT;
return PAGE_SHIFT;
}
static inline unsigned long tlb_get_unmap_size(struct mmu_gather *tlb)
{
return 1UL << tlb_get_unmap_shift(tlb);
}
/*
* In the case of tlb vma handling, we can optimise these away in the
* case where we're doing a full MM flush. When we're doing a munmap,
@@ -219,13 +264,19 @@ static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb,
#define tlb_remove_tlb_entry(tlb, ptep, address) \
do { \
__tlb_adjust_range(tlb, address, PAGE_SIZE); \
tlb->cleared_ptes = 1; \
__tlb_remove_tlb_entry(tlb, ptep, address); \
} while (0)
#define tlb_remove_huge_tlb_entry(h, tlb, ptep, address) \
do { \
__tlb_adjust_range(tlb, address, huge_page_size(h)); \
__tlb_remove_tlb_entry(tlb, ptep, address); \
#define tlb_remove_huge_tlb_entry(h, tlb, ptep, address) \
do { \
unsigned long _sz = huge_page_size(h); \
__tlb_adjust_range(tlb, address, _sz); \
if (_sz == PMD_SIZE) \
tlb->cleared_pmds = 1; \
else if (_sz == PUD_SIZE) \
tlb->cleared_puds = 1; \
__tlb_remove_tlb_entry(tlb, ptep, address); \
} while (0)
/**
@@ -239,6 +290,7 @@ static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb,
#define tlb_remove_pmd_tlb_entry(tlb, pmdp, address) \
do { \
__tlb_adjust_range(tlb, address, HPAGE_PMD_SIZE); \
tlb->cleared_pmds = 1; \
__tlb_remove_pmd_tlb_entry(tlb, pmdp, address); \
} while (0)
@@ -253,6 +305,7 @@ static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb,
#define tlb_remove_pud_tlb_entry(tlb, pudp, address) \
do { \
__tlb_adjust_range(tlb, address, HPAGE_PUD_SIZE); \
tlb->cleared_puds = 1; \
__tlb_remove_pud_tlb_entry(tlb, pudp, address); \
} while (0)
@@ -278,6 +331,8 @@ static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb,
#define pte_free_tlb(tlb, ptep, address) \
do { \
__tlb_adjust_range(tlb, address, PAGE_SIZE); \
tlb->freed_tables = 1; \
tlb->cleared_pmds = 1; \
__pte_free_tlb(tlb, ptep, address); \
} while (0)
#endif
@@ -285,7 +340,9 @@ static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb,
#ifndef pmd_free_tlb
#define pmd_free_tlb(tlb, pmdp, address) \
do { \
__tlb_adjust_range(tlb, address, PAGE_SIZE); \
__tlb_adjust_range(tlb, address, PAGE_SIZE); \
tlb->freed_tables = 1; \
tlb->cleared_puds = 1; \
__pmd_free_tlb(tlb, pmdp, address); \
} while (0)
#endif
@@ -295,6 +352,8 @@ static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb,
#define pud_free_tlb(tlb, pudp, address) \
do { \
__tlb_adjust_range(tlb, address, PAGE_SIZE); \
tlb->freed_tables = 1; \
tlb->cleared_p4ds = 1; \
__pud_free_tlb(tlb, pudp, address); \
} while (0)
#endif
@@ -304,12 +363,15 @@ static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb,
#ifndef p4d_free_tlb
#define p4d_free_tlb(tlb, pudp, address) \
do { \
__tlb_adjust_range(tlb, address, PAGE_SIZE); \
__tlb_adjust_range(tlb, address, PAGE_SIZE); \
tlb->freed_tables = 1; \
__p4d_free_tlb(tlb, pudp, address); \
} while (0)
#endif
#endif
#endif /* CONFIG_MMU */
#define tlb_migrate_finish(mm) do {} while (0)
#endif /* _ASM_GENERIC__TLB_H */

13
include/asm-generic/unistd.h
View File

@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <uapi/asm-generic/unistd.h>
#include <linux/export.h>
/*
* These are required system calls, we should
* invert the logic eventually and let them
* be selected by default.
*/
#if __BITS_PER_LONG == 32
#define __ARCH_WANT_STAT64
#define __ARCH_WANT_SYS_LLSEEK
#endif

42
include/asm-generic/vmlinux.lds.h
View File

@@ -68,7 +68,7 @@
*/
#ifdef CONFIG_LD_DEAD_CODE_DATA_ELIMINATION
#define TEXT_MAIN .text .text.[0-9a-zA-Z_]*
#define DATA_MAIN .data .data.[0-9a-zA-Z_]*
#define DATA_MAIN .data .data.[0-9a-zA-Z_]* .data..LPBX*
#define SDATA_MAIN .sdata .sdata.[0-9a-zA-Z_]*
#define RODATA_MAIN .rodata .rodata.[0-9a-zA-Z_]*
#define BSS_MAIN .bss .bss.[0-9a-zA-Z_]*
@@ -203,6 +203,15 @@
#define EARLYCON_TABLE()
#endif
#ifdef CONFIG_SECURITY
#define LSM_TABLE() . = ALIGN(8); \
__start_lsm_info = .; \
KEEP(*(.lsm_info.init)) \
__end_lsm_info = .;
#else
#define LSM_TABLE()
#endif
#define ___OF_TABLE(cfg, name) _OF_TABLE_##cfg(name)
#define __OF_TABLE(cfg, name) ___OF_TABLE(cfg, name)
#define OF_TABLE(cfg, name) __OF_TABLE(IS_ENABLED(cfg), name)
@@ -253,10 +262,6 @@
STRUCT_ALIGN(); \
*(__tracepoints) \
/* implement dynamic printk debug */ \
. = ALIGN(8); \
__start___jump_table = .; \
KEEP(*(__jump_table)) \
__stop___jump_table = .; \
. = ALIGN(8); \
__start___verbose = .; \
KEEP(*(__verbose)) \
@@ -300,6 +305,12 @@
. = __start_init_task + THREAD_SIZE; \
__end_init_task = .;
#define JUMP_TABLE_DATA \
. = ALIGN(8); \
__start___jump_table = .; \
KEEP(*(__jump_table)) \
__stop___jump_table = .;
/*
* Allow architectures to handle ro_after_init data on their
* own by defining an empty RO_AFTER_INIT_DATA.
@@ -308,6 +319,7 @@
#define RO_AFTER_INIT_DATA \
__start_ro_after_init = .; \
*(.data..ro_after_init) \
JUMP_TABLE_DATA \
__end_ro_after_init = .;
#endif
@@ -473,13 +485,6 @@
#define RODATA RO_DATA_SECTION(4096)
#define RO_DATA(align) RO_DATA_SECTION(align)
#define SECURITY_INIT \
.security_initcall.init : AT(ADDR(.security_initcall.init) - LOAD_OFFSET) { \
__security_initcall_start = .; \
KEEP(*(.security_initcall.init)) \
__security_initcall_end = .; \
}
/*
* .text section. Map to function alignment to avoid address changes
* during second ld run in second ld pass when generating System.map
@@ -604,7 +609,8 @@
IRQCHIP_OF_MATCH_TABLE() \
ACPI_PROBE_TABLE(irqchip) \
ACPI_PROBE_TABLE(timer) \
EARLYCON_TABLE()
EARLYCON_TABLE() \
LSM_TABLE()
#define INIT_TEXT \
*(.init.text .init.text.*) \
@@ -613,8 +619,8 @@
#define EXIT_DATA \
*(.exit.data .exit.data.*) \
*(.fini_array) \
*(.dtors) \
*(.fini_array .fini_array.*) \
*(.dtors .dtors.*) \
MEM_DISCARD(exit.data*) \
MEM_DISCARD(exit.rodata*)
@@ -793,11 +799,6 @@
KEEP(*(.con_initcall.init)) \
__con_initcall_end = .;
#define SECURITY_INITCALL \
__security_initcall_start = .; \
KEEP(*(.security_initcall.init)) \
__security_initcall_end = .;
#ifdef CONFIG_BLK_DEV_INITRD
#define INIT_RAM_FS \
. = ALIGN(4); \
@@ -964,7 +965,6 @@
INIT_SETUP(initsetup_align) \
INIT_CALLS \
CON_INITCALL \
SECURITY_INITCALL \
INIT_RAM_FS \
}

38
include/crypto/acompress.h
View File

@@ -234,6 +234,34 @@ static inline void acomp_request_set_params(struct acomp_req *req,
req->flags |= CRYPTO_ACOMP_ALLOC_OUTPUT;
}
static inline void crypto_stat_compress(struct acomp_req *req, int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_acomp *tfm = crypto_acomp_reqtfm(req);
if (ret && ret != -EINPROGRESS && ret != -EBUSY) {
atomic_inc(&tfm->base.__crt_alg->compress_err_cnt);
} else {
atomic_inc(&tfm->base.__crt_alg->compress_cnt);
atomic64_add(req->slen, &tfm->base.__crt_alg->compress_tlen);
}
#endif
}
static inline void crypto_stat_decompress(struct acomp_req *req, int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_acomp *tfm = crypto_acomp_reqtfm(req);
if (ret && ret != -EINPROGRESS && ret != -EBUSY) {
atomic_inc(&tfm->base.__crt_alg->compress_err_cnt);
} else {
atomic_inc(&tfm->base.__crt_alg->decompress_cnt);
atomic64_add(req->slen, &tfm->base.__crt_alg->decompress_tlen);
}
#endif
}
/**
* crypto_acomp_compress() -- Invoke asynchronous compress operation
*
@@ -246,8 +274,11 @@ static inline void acomp_request_set_params(struct acomp_req *req,
static inline int crypto_acomp_compress(struct acomp_req *req)
{
struct crypto_acomp *tfm = crypto_acomp_reqtfm(req);
int ret;
return tfm->compress(req);
ret = tfm->compress(req);
crypto_stat_compress(req, ret);
return ret;
}
/**
@@ -262,8 +293,11 @@ static inline int crypto_acomp_compress(struct acomp_req *req)
static inline int crypto_acomp_decompress(struct acomp_req *req)
{
struct crypto_acomp *tfm = crypto_acomp_reqtfm(req);
int ret;
return tfm->decompress(req);
ret = tfm->decompress(req);
crypto_stat_decompress(req, ret);
return ret;
}
#endif

51
include/crypto/aead.h
View File

@@ -306,6 +306,34 @@ static inline struct crypto_aead *crypto_aead_reqtfm(struct aead_request *req)
return __crypto_aead_cast(req->base.tfm);
}
static inline void crypto_stat_aead_encrypt(struct aead_request *req, int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
if (ret && ret != -EINPROGRESS && ret != -EBUSY) {
atomic_inc(&tfm->base.__crt_alg->aead_err_cnt);
} else {
atomic_inc(&tfm->base.__crt_alg->encrypt_cnt);
atomic64_add(req->cryptlen, &tfm->base.__crt_alg->encrypt_tlen);
}
#endif
}
static inline void crypto_stat_aead_decrypt(struct aead_request *req, int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
if (ret && ret != -EINPROGRESS && ret != -EBUSY) {
atomic_inc(&tfm->base.__crt_alg->aead_err_cnt);
} else {
atomic_inc(&tfm->base.__crt_alg->decrypt_cnt);
atomic64_add(req->cryptlen, &tfm->base.__crt_alg->decrypt_tlen);
}
#endif
}
/**
* crypto_aead_encrypt() - encrypt plaintext
* @req: reference to the aead_request handle that holds all information
@@ -328,11 +356,14 @@ static inline struct crypto_aead *crypto_aead_reqtfm(struct aead_request *req)
static inline int crypto_aead_encrypt(struct aead_request *req)
{
struct crypto_aead *aead = crypto_aead_reqtfm(req);
int ret;
if (crypto_aead_get_flags(aead) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
return crypto_aead_alg(aead)->encrypt(req);
ret = -ENOKEY;
else
ret = crypto_aead_alg(aead)->encrypt(req);
crypto_stat_aead_encrypt(req, ret);
return ret;
}
/**
@@ -360,14 +391,16 @@ static inline int crypto_aead_encrypt(struct aead_request *req)
static inline int crypto_aead_decrypt(struct aead_request *req)
{
struct crypto_aead *aead = crypto_aead_reqtfm(req);
int ret;
if (crypto_aead_get_flags(aead) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
if (req->cryptlen < crypto_aead_authsize(aead))
return -EINVAL;
return crypto_aead_alg(aead)->decrypt(req);
ret = -ENOKEY;
else if (req->cryptlen < crypto_aead_authsize(aead))
ret = -EINVAL;
else
ret = crypto_aead_alg(aead)->decrypt(req);
crypto_stat_aead_decrypt(req, ret);
return ret;
}
/**

76
include/crypto/akcipher.h
View File

@@ -271,6 +271,62 @@ static inline unsigned int crypto_akcipher_maxsize(struct crypto_akcipher *tfm)
return alg->max_size(tfm);
}
static inline void crypto_stat_akcipher_encrypt(struct akcipher_request *req,
int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
if (ret && ret != -EINPROGRESS && ret != -EBUSY) {
atomic_inc(&tfm->base.__crt_alg->akcipher_err_cnt);
} else {
atomic_inc(&tfm->base.__crt_alg->encrypt_cnt);
atomic64_add(req->src_len, &tfm->base.__crt_alg->encrypt_tlen);
}
#endif
}
static inline void crypto_stat_akcipher_decrypt(struct akcipher_request *req,
int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
if (ret && ret != -EINPROGRESS && ret != -EBUSY) {
atomic_inc(&tfm->base.__crt_alg->akcipher_err_cnt);
} else {
atomic_inc(&tfm->base.__crt_alg->decrypt_cnt);
atomic64_add(req->src_len, &tfm->base.__crt_alg->decrypt_tlen);
}
#endif
}
static inline void crypto_stat_akcipher_sign(struct akcipher_request *req,
int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
if (ret && ret != -EINPROGRESS && ret != -EBUSY)
atomic_inc(&tfm->base.__crt_alg->akcipher_err_cnt);
else
atomic_inc(&tfm->base.__crt_alg->sign_cnt);
#endif
}
static inline void crypto_stat_akcipher_verify(struct akcipher_request *req,
int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
if (ret && ret != -EINPROGRESS && ret != -EBUSY)
atomic_inc(&tfm->base.__crt_alg->akcipher_err_cnt);
else
atomic_inc(&tfm->base.__crt_alg->verify_cnt);
#endif
}
/**
* crypto_akcipher_encrypt() - Invoke public key encrypt operation
*
@@ -285,8 +341,11 @@ static inline int crypto_akcipher_encrypt(struct akcipher_request *req)
{
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
struct akcipher_alg *alg = crypto_akcipher_alg(tfm);
int ret;
return alg->encrypt(req);
ret = alg->encrypt(req);
crypto_stat_akcipher_encrypt(req, ret);
return ret;
}
/**
@@ -303,8 +362,11 @@ static inline int crypto_akcipher_decrypt(struct akcipher_request *req)
{
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
struct akcipher_alg *alg = crypto_akcipher_alg(tfm);
int ret;
return alg->decrypt(req);
ret = alg->decrypt(req);
crypto_stat_akcipher_decrypt(req, ret);
return ret;
}
/**
@@ -321,8 +383,11 @@ static inline int crypto_akcipher_sign(struct akcipher_request *req)
{
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
struct akcipher_alg *alg = crypto_akcipher_alg(tfm);
int ret;
return alg->sign(req);
ret = alg->sign(req);
crypto_stat_akcipher_sign(req, ret);
return ret;
}
/**
@@ -339,8 +404,11 @@ static inline int crypto_akcipher_verify(struct akcipher_request *req)
{
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
struct akcipher_alg *alg = crypto_akcipher_alg(tfm);
int ret;
return alg->verify(req);
ret = alg->verify(req);
crypto_stat_akcipher_verify(req, ret);
return ret;
}
/**

14
include/crypto/algapi.h
View File

@@ -20,8 +20,10 @@
/*
* Maximum values for blocksize and alignmask, used to allocate
* static buffers that are big enough for any combination of
* ciphers and architectures.
* algs and architectures. Ciphers have a lower maximum size.
*/
#define MAX_ALGAPI_BLOCKSIZE 160
#define MAX_ALGAPI_ALIGNMASK 63
#define MAX_CIPHER_BLOCKSIZE 16
#define MAX_CIPHER_ALIGNMASK 15
@@ -425,4 +427,14 @@ static inline void crypto_yield(u32 flags)
#endif
}
int crypto_register_notifier(struct notifier_block *nb);
int crypto_unregister_notifier(struct notifier_block *nb);
/* Crypto notification events. */
enum {
CRYPTO_MSG_ALG_REQUEST,
CRYPTO_MSG_ALG_REGISTER,
CRYPTO_MSG_ALG_LOADED,
};
#endif /* _CRYPTO_ALGAPI_H */

19
include/crypto/asym_tpm_subtype.h Normal file
View File

@@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
#ifndef _LINUX_ASYM_TPM_SUBTYPE_H
#define _LINUX_ASYM_TPM_SUBTYPE_H
#include <linux/keyctl.h>
struct tpm_key {
void *blob;
u32 blob_len;
uint16_t key_len; /* Size in bits of the key */
const void *pub_key; /* pointer inside blob to the public key bytes */
uint16_t pub_key_len; /* length of the public key */
};
struct tpm_key *tpm_key_create(const void *blob, uint32_t blob_len);
extern struct asymmetric_key_subtype asym_tpm_subtype;
#endif /* _LINUX_ASYM_TPM_SUBTYPE_H */

2
include/crypto/cbc.h
View File

@@ -113,7 +113,7 @@ static inline int crypto_cbc_decrypt_inplace(
unsigned int bsize = crypto_skcipher_blocksize(tfm);
unsigned int nbytes = walk->nbytes;
u8 *src = walk->src.virt.addr;
u8 last_iv[bsize];
u8 last_iv[MAX_CIPHER_BLOCKSIZE];
/* Start of the last block. */
src += nbytes - (nbytes & (bsize - 1)) - bsize;

3
include/crypto/chacha20.h
View File

@@ -13,13 +13,12 @@
#define CHACHA20_IV_SIZE 16
#define CHACHA20_KEY_SIZE 32
#define CHACHA20_BLOCK_SIZE 64
#define CHACHA20_BLOCK_WORDS (CHACHA20_BLOCK_SIZE / sizeof(u32))
struct chacha20_ctx {
u32 key[8];
};
void chacha20_block(u32 *state, u32 *stream);
void chacha20_block(u32 *state, u8 *stream);
void crypto_chacha20_init(u32 *state, struct chacha20_ctx *ctx, u8 *iv);
int crypto_chacha20_setkey(struct crypto_skcipher *tfm, const u8 *key,
unsigned int keysize);

38
include/crypto/hash.h
View File

@@ -151,9 +151,13 @@ struct shash_desc {
void *__ctx[] CRYPTO_MINALIGN_ATTR;
};
#define HASH_MAX_DIGESTSIZE 64
#define HASH_MAX_DESCSIZE 360
#define HASH_MAX_STATESIZE 512
#define SHASH_DESC_ON_STACK(shash, ctx) \
char __##shash##_desc[sizeof(struct shash_desc) + \
crypto_shash_descsize(ctx)] CRYPTO_MINALIGN_ATTR; \
HASH_MAX_DESCSIZE] CRYPTO_MINALIGN_ATTR; \
struct shash_desc *shash = (struct shash_desc *)__##shash##_desc
/**
@@ -408,6 +412,32 @@ static inline void *ahash_request_ctx(struct ahash_request *req)
int crypto_ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
unsigned int keylen);
static inline void crypto_stat_ahash_update(struct ahash_request *req, int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
if (ret && ret != -EINPROGRESS && ret != -EBUSY)
atomic_inc(&tfm->base.__crt_alg->hash_err_cnt);
else
atomic64_add(req->nbytes, &tfm->base.__crt_alg->hash_tlen);
#endif
}
static inline void crypto_stat_ahash_final(struct ahash_request *req, int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
if (ret && ret != -EINPROGRESS && ret != -EBUSY) {
atomic_inc(&tfm->base.__crt_alg->hash_err_cnt);
} else {
atomic_inc(&tfm->base.__crt_alg->hash_cnt);
atomic64_add(req->nbytes, &tfm->base.__crt_alg->hash_tlen);
}
#endif
}
/**
* crypto_ahash_finup() - update and finalize message digest
* @req: reference to the ahash_request handle that holds all information
@@ -522,7 +552,11 @@ static inline int crypto_ahash_init(struct ahash_request *req)
*/
static inline int crypto_ahash_update(struct ahash_request *req)
{
return crypto_ahash_reqtfm(req)->update(req);
int ret;
ret = crypto_ahash_reqtfm(req)->update(req);
crypto_stat_ahash_update(req, ret);
return ret;
}
/**

8
include/crypto/internal/cryptouser.h Normal file
View File

@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <net/netlink.h>
struct crypto_alg *crypto_alg_match(struct crypto_user_alg *p, int exact);
int crypto_dump_reportstat(struct sk_buff *skb, struct netlink_callback *cb);
int crypto_reportstat(struct sk_buff *in_skb, struct nlmsghdr *in_nlh, struct nlattr **attrs);
int crypto_dump_reportstat_done(struct netlink_callback *cb);

2
include/crypto/internal/geniv.h
View File

@@ -20,7 +20,7 @@
struct aead_geniv_ctx {
spinlock_t lock;
struct crypto_aead *child;
struct crypto_skcipher *sknull;
struct crypto_sync_skcipher *sknull;
u8 salt[] __attribute__ ((aligned(__alignof__(u32))));
};

51
include/crypto/kpp.h
View File

@@ -268,6 +268,42 @@ struct kpp_secret {
unsigned short len;
};
static inline void crypto_stat_kpp_set_secret(struct crypto_kpp *tfm, int ret)
{
#ifdef CONFIG_CRYPTO_STATS
if (ret)
atomic_inc(&tfm->base.__crt_alg->kpp_err_cnt);
else
atomic_inc(&tfm->base.__crt_alg->setsecret_cnt);
#endif
}
static inline void crypto_stat_kpp_generate_public_key(struct kpp_request *req,
int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_kpp *tfm = crypto_kpp_reqtfm(req);
if (ret)
atomic_inc(&tfm->base.__crt_alg->kpp_err_cnt);
else
atomic_inc(&tfm->base.__crt_alg->generate_public_key_cnt);
#endif
}
static inline void crypto_stat_kpp_compute_shared_secret(struct kpp_request *req,
int ret)
{
#ifdef CONFIG_CRYPTO_STATS
struct crypto_kpp *tfm = crypto_kpp_reqtfm(req);
if (ret)
atomic_inc(&tfm->base.__crt_alg->kpp_err_cnt);
else
atomic_inc(&tfm->base.__crt_alg->compute_shared_secret_cnt);
#endif
}
/**
* crypto_kpp_set_secret() - Invoke kpp operation
*
@@ -287,8 +323,11 @@ static inline int crypto_kpp_set_secret(struct crypto_kpp *tfm,
const void *buffer, unsigned int len)
{
struct kpp_alg *alg = crypto_kpp_alg(tfm);
int ret;
return alg->set_secret(tfm, buffer, len);
ret = alg->set_secret(tfm, buffer, len);
crypto_stat_kpp_set_secret(tfm, ret);
return ret;
}
/**
@@ -308,8 +347,11 @@ static inline int crypto_kpp_generate_public_key(struct kpp_request *req)
{
struct crypto_kpp *tfm = crypto_kpp_reqtfm(req);
struct kpp_alg *alg = crypto_kpp_alg(tfm);
int ret;
return alg->generate_public_key(req);
ret = alg->generate_public_key(req);
crypto_stat_kpp_generate_public_key(req, ret);
return ret;
}
/**
@@ -326,8 +368,11 @@ static inline int crypto_kpp_compute_shared_secret(struct kpp_request *req)
{
struct crypto_kpp *tfm = crypto_kpp_reqtfm(req);
struct kpp_alg *alg = crypto_kpp_alg(tfm);
int ret;
return alg->compute_shared_secret(req);
ret = alg->compute_shared_secret(req);
crypto_stat_kpp_compute_shared_secret(req, ret);
return ret;
}
/**

114
include/crypto/mcryptd.h
View File

@@ -1,114 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Software async multibuffer crypto daemon headers
*
* Author:
* Tim Chen <tim.c.chen@linux.intel.com>
*
* Copyright (c) 2014, Intel Corporation.
*/
#ifndef _CRYPTO_MCRYPT_H
#define _CRYPTO_MCRYPT_H
#include <linux/crypto.h>
#include <linux/kernel.h>
#include <crypto/hash.h>
struct mcryptd_ahash {
struct crypto_ahash base;
};
static inline struct mcryptd_ahash *__mcryptd_ahash_cast(
struct crypto_ahash *tfm)
{
return (struct mcryptd_ahash *)tfm;
}
struct mcryptd_cpu_queue {
struct crypto_queue queue;
spinlock_t q_lock;
struct work_struct work;
};
struct mcryptd_queue {
struct mcryptd_cpu_queue __percpu *cpu_queue;
};
struct mcryptd_instance_ctx {
struct crypto_spawn spawn;
struct mcryptd_queue *queue;
};
struct mcryptd_hash_ctx {
struct crypto_ahash *child;
struct mcryptd_alg_state *alg_state;
};
struct mcryptd_tag {
/* seq number of request */
unsigned seq_num;
/* arrival time of request */
unsigned long arrival;
unsigned long expire;
int cpu;
};
struct mcryptd_hash_request_ctx {
struct list_head waiter;
crypto_completion_t complete;
struct mcryptd_tag tag;
struct crypto_hash_walk walk;
u8 *out;
int flag;
struct ahash_request areq;
};
struct mcryptd_ahash *mcryptd_alloc_ahash(const char *alg_name,
u32 type, u32 mask);
struct crypto_ahash *mcryptd_ahash_child(struct mcryptd_ahash *tfm);
struct ahash_request *mcryptd_ahash_desc(struct ahash_request *req);
void mcryptd_free_ahash(struct mcryptd_ahash *tfm);
void mcryptd_flusher(struct work_struct *work);
enum mcryptd_req_type {
MCRYPTD_NONE,
MCRYPTD_UPDATE,
MCRYPTD_FINUP,
MCRYPTD_DIGEST,
MCRYPTD_FINAL
};
struct mcryptd_alg_cstate {
unsigned long next_flush;
unsigned next_seq_num;
bool flusher_engaged;
struct delayed_work flush;
int cpu;
struct mcryptd_alg_state *alg_state;
void *mgr;
spinlock_t work_lock;
struct list_head work_list;
struct list_head flush_list;
};
struct mcryptd_alg_state {
struct mcryptd_alg_cstate __percpu *alg_cstate;
unsigned long (*flusher)(struct mcryptd_alg_cstate *cstate);
};
/* return delay in jiffies from current time */
static inline unsigned long get_delay(unsigned long t)
{
long delay;
delay = (long) t - (long) jiffies;
if (delay <= 0)
return 0;
else
return (unsigned long) delay;
}
void mcryptd_arm_flusher(struct mcryptd_alg_cstate *cstate, unsigned long delay);
#endif

2
include/crypto/morus1280_glue.h
View File

@@ -82,7 +82,7 @@ void cryptd_morus1280_glue_exit_tfm(struct crypto_aead *aead);
{ \
} \
\
struct aead_alg crypto_morus1280_##id##_algs[] = {\
static struct aead_alg crypto_morus1280_##id##_algs[] = {\
{ \
.setkey = crypto_morus1280_glue_setkey, \
.setauthsize = crypto_morus1280_glue_setauthsize, \

2
include/crypto/morus640_glue.h
View File

@@ -82,7 +82,7 @@ void cryptd_morus640_glue_exit_tfm(struct crypto_aead *aead);
{ \
} \
\
struct aead_alg crypto_morus640_##id##_algs[] = {\
static struct aead_alg crypto_morus640_##id##_algs[] = {\
{ \
.setkey = crypto_morus640_glue_setkey, \
.setauthsize = crypto_morus640_glue_setauthsize, \

2
include/crypto/null.h
View File

@@ -9,7 +9,7 @@
#define NULL_DIGEST_SIZE 0
#define NULL_IV_SIZE 0
struct crypto_skcipher *crypto_get_default_null_skcipher(void);
struct crypto_sync_skcipher *crypto_get_default_null_skcipher(void);
void crypto_put_default_null_skcipher(void);
#endif

14
include/crypto/public_key.h
View File

@@ -14,6 +14,8 @@
#ifndef _LINUX_PUBLIC_KEY_H
#define _LINUX_PUBLIC_KEY_H
#include <linux/keyctl.h>
/*
* Cryptographic data for the public-key subtype of the asymmetric key type.
*
@@ -23,6 +25,7 @@
struct public_key {
void *key;
u32 keylen;
bool key_is_private;
const char *id_type;
const char *pkey_algo;
};
@@ -40,6 +43,7 @@ struct public_key_signature {
u8 digest_size; /* Number of bytes in digest */
const char *pkey_algo;
const char *hash_algo;
const char *encoding;
};
extern void public_key_signature_free(struct public_key_signature *sig);
@@ -65,8 +69,14 @@ extern int restrict_link_by_key_or_keyring_chain(struct key *trust_keyring,
const union key_payload *payload,
struct key *trusted);
extern int verify_signature(const struct key *key,
const struct public_key_signature *sig);
extern int query_asymmetric_key(const struct kernel_pkey_params *,
struct kernel_pkey_query *);
extern int encrypt_blob(struct kernel_pkey_params *, const void *, void *);
extern int decrypt_blob(struct kernel_pkey_params *, const void *, void *);
extern int create_signature(struct kernel_pkey_params *, const void *, void *);
extern int verify_signature(const struct key *,
const struct public_key_signature *);
int public_key_verify_signature(const struct public_key *pkey,
const struct public_key_signature *sig);

29
include/crypto/rng.h
View File

@@ -122,6 +122,29 @@ static inline void crypto_free_rng(struct crypto_rng *tfm)
crypto_destroy_tfm(tfm, crypto_rng_tfm(tfm));
}
static inline void crypto_stat_rng_seed(struct crypto_rng *tfm, int ret)
{
#ifdef CONFIG_CRYPTO_STATS
if (ret && ret != -EINPROGRESS && ret != -EBUSY)
atomic_inc(&tfm->base.__crt_alg->rng_err_cnt);
else
atomic_inc(&tfm->base.__crt_alg->seed_cnt);
#endif
}
static inline void crypto_stat_rng_generate(struct crypto_rng *tfm,
unsigned int dlen, int ret)
{
#ifdef CONFIG_CRYPTO_STATS
if (ret && ret != -EINPROGRESS && ret != -EBUSY) {
atomic_inc(&tfm->base.__crt_alg->rng_err_cnt);
} else {
atomic_inc(&tfm->base.__crt_alg->generate_cnt);
atomic64_add(dlen, &tfm->base.__crt_alg->generate_tlen);
}
#endif
}
/**
* crypto_rng_generate() - get random number
* @tfm: cipher handle
@@ -140,7 +163,11 @@ static inline int crypto_rng_generate(struct crypto_rng *tfm,
const u8 *src, unsigned int slen,
u8 *dst, unsigned int dlen)
{
return crypto_rng_alg(tfm)->generate(tfm, src, slen, dst, dlen);
int ret;
ret = crypto_rng_alg(tfm)->generate(tfm, src, slen, dst, dlen);
crypto_stat_rng_generate(tfm, dlen, ret);
return ret;
}
/**

118
include/crypto/skcipher.h
View File

@@ -65,6 +65,10 @@ struct crypto_skcipher {
struct crypto_tfm base;
};
struct crypto_sync_skcipher {
struct crypto_skcipher base;
};
/**
* struct skcipher_alg - symmetric key cipher definition
* @min_keysize: Minimum key size supported by the transformation. This is the
@@ -139,9 +143,17 @@ struct skcipher_alg {
struct crypto_alg base;
};
#define SKCIPHER_REQUEST_ON_STACK(name, tfm) \
#define MAX_SYNC_SKCIPHER_REQSIZE 384
/*
* This performs a type-check against the "tfm" argument to make sure
* all users have the correct skcipher tfm for doing on-stack requests.
*/
#define SYNC_SKCIPHER_REQUEST_ON_STACK(name, tfm) \
char __##name##_desc[sizeof(struct skcipher_request) + \
crypto_skcipher_reqsize(tfm)] CRYPTO_MINALIGN_ATTR; \
MAX_SYNC_SKCIPHER_REQSIZE + \
(!(sizeof((struct crypto_sync_skcipher *)1 == \
(typeof(tfm))1))) \
] CRYPTO_MINALIGN_ATTR; \
struct skcipher_request *name = (void *)__##name##_desc
/**
@@ -197,6 +209,9 @@ static inline struct crypto_skcipher *__crypto_skcipher_cast(
struct crypto_skcipher *crypto_alloc_skcipher(const char *alg_name,
u32 type, u32 mask);
struct crypto_sync_skcipher *crypto_alloc_sync_skcipher(const char *alg_name,
u32 type, u32 mask);
static inline struct crypto_tfm *crypto_skcipher_tfm(
struct crypto_skcipher *tfm)
{
@@ -212,6 +227,11 @@ static inline void crypto_free_skcipher(struct crypto_skcipher *tfm)
crypto_destroy_tfm(tfm, crypto_skcipher_tfm(tfm));
}
static inline void crypto_free_sync_skcipher(struct crypto_sync_skcipher *tfm)
{
crypto_free_skcipher(&tfm->base);
}
/**
* crypto_has_skcipher() - Search for the availability of an skcipher.
* @alg_name: is the cra_name / name or cra_driver_name / driver name of the
@@ -280,6 +300,12 @@ static inline unsigned int crypto_skcipher_ivsize(struct crypto_skcipher *tfm)
return tfm->ivsize;
}
static inline unsigned int crypto_sync_skcipher_ivsize(
struct crypto_sync_skcipher *tfm)
{
return crypto_skcipher_ivsize(&tfm->base);
}
static inline unsigned int crypto_skcipher_alg_chunksize(
struct skcipher_alg *alg)
{
@@ -356,6 +382,12 @@ static inline unsigned int crypto_skcipher_blocksize(
return crypto_tfm_alg_blocksize(crypto_skcipher_tfm(tfm));
}
static inline unsigned int crypto_sync_skcipher_blocksize(
struct crypto_sync_skcipher *tfm)
{
return crypto_skcipher_blocksize(&tfm->base);
}
static inline unsigned int crypto_skcipher_alignmask(
struct crypto_skcipher *tfm)
{
@@ -379,6 +411,24 @@ static inline void crypto_skcipher_clear_flags(struct crypto_skcipher *tfm,
crypto_tfm_clear_flags(crypto_skcipher_tfm(tfm), flags);
}
static inline u32 crypto_sync_skcipher_get_flags(
struct crypto_sync_skcipher *tfm)
{
return crypto_skcipher_get_flags(&tfm->base);
}
static inline void crypto_sync_skcipher_set_flags(
struct crypto_sync_skcipher *tfm, u32 flags)
{
crypto_skcipher_set_flags(&tfm->base, flags);
}
static inline void crypto_sync_skcipher_clear_flags(
struct crypto_sync_skcipher *tfm, u32 flags)
{
crypto_skcipher_clear_flags(&tfm->base, flags);
}
/**
* crypto_skcipher_setkey() - set key for cipher
* @tfm: cipher handle
@@ -401,6 +451,12 @@ static inline int crypto_skcipher_setkey(struct crypto_skcipher *tfm,
return tfm->setkey(tfm, key, keylen);
}
static inline int crypto_sync_skcipher_setkey(struct crypto_sync_skcipher *tfm,
const u8 *key, unsigned int keylen)
{
return crypto_skcipher_setkey(&tfm->base, key, keylen);
}
static inline unsigned int crypto_skcipher_default_keysize(
struct crypto_skcipher *tfm)
{
@@ -422,6 +478,40 @@ static inline struct crypto_skcipher *crypto_skcipher_reqtfm(
return __crypto_skcipher_cast(req->base.tfm);
}
static inline struct crypto_sync_skcipher *crypto_sync_skcipher_reqtfm(
struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
return container_of(tfm, struct crypto_sync_skcipher, base);
}
static inline void crypto_stat_skcipher_encrypt(struct skcipher_request *req,
int ret, struct crypto_alg *alg)
{
#ifdef CONFIG_CRYPTO_STATS
if (ret && ret != -EINPROGRESS && ret != -EBUSY) {
atomic_inc(&alg->cipher_err_cnt);
} else {
atomic_inc(&alg->encrypt_cnt);
atomic64_add(req->cryptlen, &alg->encrypt_tlen);
}
#endif
}
static inline void crypto_stat_skcipher_decrypt(struct skcipher_request *req,
int ret, struct crypto_alg *alg)
{
#ifdef CONFIG_CRYPTO_STATS
if (ret && ret != -EINPROGRESS && ret != -EBUSY) {
atomic_inc(&alg->cipher_err_cnt);
} else {
atomic_inc(&alg->decrypt_cnt);
atomic64_add(req->cryptlen, &alg->decrypt_tlen);
}
#endif
}
/**
* crypto_skcipher_encrypt() - encrypt plaintext
* @req: reference to the skcipher_request handle that holds all information
@@ -436,11 +526,14 @@ static inline struct crypto_skcipher *crypto_skcipher_reqtfm(
static inline int crypto_skcipher_encrypt(struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
int ret;
if (crypto_skcipher_get_flags(tfm) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
return tfm->encrypt(req);
ret = -ENOKEY;
else
ret = tfm->encrypt(req);
crypto_stat_skcipher_encrypt(req, ret, tfm->base.__crt_alg);
return ret;
}
/**
@@ -457,11 +550,14 @@ static inline int crypto_skcipher_encrypt(struct skcipher_request *req)
static inline int crypto_skcipher_decrypt(struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
int ret;
if (crypto_skcipher_get_flags(tfm) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
return tfm->decrypt(req);
ret = -ENOKEY;
else
ret = tfm->decrypt(req);
crypto_stat_skcipher_decrypt(req, ret, tfm->base.__crt_alg);
return ret;
}
/**
@@ -500,6 +596,12 @@ static inline void skcipher_request_set_tfm(struct skcipher_request *req,
req->base.tfm = crypto_skcipher_tfm(tfm);
}
static inline void skcipher_request_set_sync_tfm(struct skcipher_request *req,
struct crypto_sync_skcipher *tfm)
{
skcipher_request_set_tfm(req, &tfm->base);
}
static inline struct skcipher_request *skcipher_request_cast(
struct crypto_async_request *req)
{

62
include/crypto/speck.h
View File

@@ -1,62 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Common values for the Speck algorithm
*/
#ifndef _CRYPTO_SPECK_H
#define _CRYPTO_SPECK_H
#include <linux/types.h>
/* Speck128 */
#define SPECK128_BLOCK_SIZE 16
#define SPECK128_128_KEY_SIZE 16
#define SPECK128_128_NROUNDS 32
#define SPECK128_192_KEY_SIZE 24
#define SPECK128_192_NROUNDS 33
#define SPECK128_256_KEY_SIZE 32
#define SPECK128_256_NROUNDS 34
struct speck128_tfm_ctx {
u64 round_keys[SPECK128_256_NROUNDS];
int nrounds;
};
void crypto_speck128_encrypt(const struct speck128_tfm_ctx *ctx,
u8 *out, const u8 *in);
void crypto_speck128_decrypt(const struct speck128_tfm_ctx *ctx,
u8 *out, const u8 *in);
int crypto_speck128_setkey(struct speck128_tfm_ctx *ctx, const u8 *key,
unsigned int keysize);
/* Speck64 */
#define SPECK64_BLOCK_SIZE 8
#define SPECK64_96_KEY_SIZE 12
#define SPECK64_96_NROUNDS 26
#define SPECK64_128_KEY_SIZE 16
#define SPECK64_128_NROUNDS 27
struct speck64_tfm_ctx {
u32 round_keys[SPECK64_128_NROUNDS];
int nrounds;
};
void crypto_speck64_encrypt(const struct speck64_tfm_ctx *ctx,
u8 *out, const u8 *in);
void crypto_speck64_decrypt(const struct speck64_tfm_ctx *ctx,
u8 *out, const u8 *in);
int crypto_speck64_setkey(struct speck64_tfm_ctx *ctx, const u8 *key,
unsigned int keysize);
#endif /* _CRYPTO_SPECK_H */

11
include/drm/drm_atomic.h
View File

@@ -154,6 +154,17 @@ struct __drm_planes_state {
struct __drm_crtcs_state {
struct drm_crtc *ptr;
struct drm_crtc_state *state, *old_state, *new_state;
/**
* @commit:
*
* A reference to the CRTC commit object that is kept for use by
* drm_atomic_helper_wait_for_flip_done() after
* drm_atomic_helper_commit_hw_done() is called. This ensures that a
* concurrent commit won't free a commit object that is still in use.
*/
struct drm_crtc_commit *commit;
s32 __user *out_fence_ptr;
u64 last_vblank_count;
};

5
include/drm/drm_client.h
View File

@@ -87,9 +87,10 @@ struct drm_client_dev {
struct drm_file *file;
};
int drm_client_new(struct drm_device *dev, struct drm_client_dev *client,
const char *name, const struct drm_client_funcs *funcs);
int drm_client_init(struct drm_device *dev, struct drm_client_dev *client,
const char *name, const struct drm_client_funcs *funcs);
void drm_client_release(struct drm_client_dev *client);
void drm_client_add(struct drm_client_dev *client);
void drm_client_dev_unregister(struct drm_device *dev);
void drm_client_dev_hotplug(struct drm_device *dev);

71
include/drm/drm_connector.h
View File

@@ -82,6 +82,53 @@ enum drm_connector_status {
connector_status_unknown = 3,
};
/**
* enum drm_connector_registration_status - userspace registration status for
* a &drm_connector
*
* This enum is used to track the status of initializing a connector and
* registering it with userspace, so that DRM can prevent bogus modesets on
* connectors that no longer exist.
*/
enum drm_connector_registration_state {
/**
* @DRM_CONNECTOR_INITIALIZING: The connector has just been created,
* but has yet to be exposed to userspace. There should be no
* additional restrictions to how the state of this connector may be
* modified.
*/
DRM_CONNECTOR_INITIALIZING = 0,
/**
* @DRM_CONNECTOR_REGISTERED: The connector has been fully initialized
* and registered with sysfs, as such it has been exposed to
* userspace. There should be no additional restrictions to how the
* state of this connector may be modified.
*/
DRM_CONNECTOR_REGISTERED = 1,
/**
* @DRM_CONNECTOR_UNREGISTERED: The connector has either been exposed
* to userspace and has since been unregistered and removed from
* userspace, or the connector was unregistered before it had a chance
* to be exposed to userspace (e.g. still in the
* @DRM_CONNECTOR_INITIALIZING state). When a connector is
* unregistered, there are additional restrictions to how its state
* may be modified:
*
* - An unregistered connector may only have its DPMS changed from
* On->Off. Once DPMS is changed to Off, it may not be switched back
* to On.
* - Modesets are not allowed on unregistered connectors, unless they
* would result in disabling its assigned CRTCs. This means
* disabling a CRTC on an unregistered connector is OK, but enabling
* one is not.
* - Removing a CRTC from an unregistered connector is OK, but new
* CRTCs may never be assigned to an unregistered connector.
*/
DRM_CONNECTOR_UNREGISTERED = 2,
};
enum subpixel_order {
SubPixelUnknown = 0,
SubPixelHorizontalRGB,
@@ -853,10 +900,12 @@ struct drm_connector {
bool ycbcr_420_allowed;
/**
* @registered: Is this connector exposed (registered) with userspace?
* @registration_state: Is this connector initializing, exposed
* (registered) with userspace, or unregistered?
*
* Protected by @mutex.
*/
bool registered;
enum drm_connector_registration_state registration_state;
/**
* @modes:
@@ -1167,6 +1216,24 @@ static inline void drm_connector_unreference(struct drm_connector *connector)
drm_connector_put(connector);
}
/**
* drm_connector_is_unregistered - has the connector been unregistered from
* userspace?
* @connector: DRM connector
*
* Checks whether or not @connector has been unregistered from userspace.
*
* Returns:
* True if the connector was unregistered, false if the connector is
* registered or has not yet been registered with userspace.
*/
static inline bool
drm_connector_is_unregistered(struct drm_connector *connector)
{
return READ_ONCE(connector->registration_state) ==
DRM_CONNECTOR_UNREGISTERED;
}
const char *drm_get_connector_status_name(enum drm_connector_status status);
const char *drm_get_subpixel_order_name(enum subpixel_order order);
const char *drm_get_dpms_name(int val);

6
include/drm/drm_edid.h
View File

@@ -214,9 +214,9 @@ struct detailed_timing {
#define DRM_EDID_HDMI_DC_Y444 (1 << 3)
/* YCBCR 420 deep color modes */
#define DRM_EDID_YCBCR420_DC_48 (1 << 6)
#define DRM_EDID_YCBCR420_DC_36 (1 << 5)
#define DRM_EDID_YCBCR420_DC_30 (1 << 4)
#define DRM_EDID_YCBCR420_DC_48 (1 << 2)
#define DRM_EDID_YCBCR420_DC_36 (1 << 1)
#define DRM_EDID_YCBCR420_DC_30 (1 << 0)
#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
DRM_EDID_YCBCR420_DC_36 | \
DRM_EDID_YCBCR420_DC_30)

119
include/dt-bindings/clock/am3.h
View File

@@ -16,6 +16,8 @@
#define AM3_CLKCTRL_OFFSET 0x0
#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* l4_per clocks */
#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
@@ -105,4 +107,121 @@
#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
/* XXX: Compatibility part end */
/* l4ls clocks */
#define AM3_L4LS_CLKCTRL_OFFSET 0x38
#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38)
#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c)
#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40)
#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44)
#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48)
#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c)
#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50)
#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60)
#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c)
#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70)
#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74)
#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78)
#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c)
#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80)
#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84)
#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88)
#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90)
#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac)
#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0)
#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4)
#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0)
#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4)
#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc)
#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4)
#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8)
#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec)
#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0)
#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4)
#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c)
#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110)
#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130)
/* l3s clocks */
#define AM3_L3S_CLKCTRL_OFFSET 0x1c
#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET)
#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c)
#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30)
#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34)
#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68)
#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8)
/* l3 clocks */
#define AM3_L3_CLKCTRL_OFFSET 0x24
#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET)
#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24)
#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28)
#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c)
#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94)
#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0)
#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc)
#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc)
#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0)
#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc)
#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100)
/* l4hs clocks */
#define AM3_L4HS_CLKCTRL_OFFSET 0x120
#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET)
#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120)
/* pruss_ocp clocks */
#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8
#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
/* cpsw_125mhz clocks */
#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14)
/* lcdc clocks */
#define AM3_LCDC_CLKCTRL_OFFSET 0x18
#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET)
#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18)
/* clk_24mhz clocks */
#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c
#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
/* l4_wkup clocks */
#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8)
#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc)
#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4)
#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8)
#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc)
#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0)
#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4)
#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8)
#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4)
/* l3_aon clocks */
#define AM3_L3_AON_CLKCTRL_OFFSET 0x14
#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14)
/* l4_wkup_aon clocks */
#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0
#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
/* mpu clocks */
#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
/* l4_rtc clocks */
#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
/* gfx_l3 clocks */
#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
/* l4_cefuse clocks */
#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20)
#endif

132
include/dt-bindings/clock/am4.h
View File

@@ -16,6 +16,8 @@
#define AM4_CLKCTRL_OFFSET 0x20
#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* l4_wkup clocks */
#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
@@ -110,4 +112,134 @@
#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
/* XXX: Compatibility part end. */
/* l3s_tsc clocks */
#define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
#define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)
#define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
/* l4_wkup_aon clocks */
#define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
#define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET)
#define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
#define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
/* l4_wkup clocks */
#define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
#define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET)
#define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
#define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
#define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
#define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340)
#define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348)
#define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350)
#define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358)
#define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360)
#define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368)
/* mpu clocks */
#define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* gfx_l3 clocks */
#define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* l4_rtc clocks */
#define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* l3 clocks */
#define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
#define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
#define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
#define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
#define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
#define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
#define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
#define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
#define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
#define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
#define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
/* l3s clocks */
#define AM4_L3S_CLKCTRL_OFFSET 0x68
#define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET)
#define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68)
#define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70)
#define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220)
#define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238)
#define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240)
#define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248)
#define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258)
#define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260)
#define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268)
/* pruss_ocp clocks */
#define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320
#define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET)
#define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320)
/* l4ls clocks */
#define AM4_L4LS_CLKCTRL_OFFSET 0x420
#define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET)
#define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420)
#define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428)
#define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430)
#define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438)
#define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440)
#define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448)
#define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450)
#define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458)
#define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460)
#define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468)
#define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478)
#define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480)
#define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488)
#define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490)
#define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498)
#define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0)
#define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8)
#define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0)
#define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8)
#define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0)
#define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8)
#define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0)
#define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500)
#define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508)
#define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510)
#define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518)
#define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520)
#define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528)
#define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530)
#define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538)
#define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540)
#define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548)
#define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550)
#define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558)
#define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560)
#define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568)
#define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570)
#define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578)
#define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580)
#define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588)
#define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590)
#define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598)
#define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0)
#define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8)
#define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0)
/* emif clocks */
#define AM4_EMIF_CLKCTRL_OFFSET 0x720
#define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET)
#define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720)
/* dss clocks */
#define AM4_DSS_CLKCTRL_OFFSET 0xa20
#define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET)
#define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20)
/* cpsw_125mhz clocks */
#define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20
#define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET)
#define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20)
#endif

15
include/dt-bindings/clock/at91.h
View File

@@ -9,6 +9,20 @@
#ifndef _DT_BINDINGS_CLK_AT91_H
#define _DT_BINDINGS_CLK_AT91_H
#define PMC_TYPE_CORE 0
#define PMC_TYPE_SYSTEM 1
#define PMC_TYPE_PERIPHERAL 2
#define PMC_TYPE_GCK 3
#define PMC_SLOW 0
#define PMC_MCK 1
#define PMC_UTMI 2
#define PMC_MAIN 3
#define PMC_MCK2 4
#define PMC_I2S0_MUX 5
#define PMC_I2S1_MUX 6
#ifndef AT91_PMC_MOSCS
#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
#define AT91_PMC_LOCKA 1 /* PLLA Lock */
#define AT91_PMC_LOCKB 2 /* PLLB Lock */
@@ -19,5 +33,6 @@
#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
#define AT91_PMC_GCKRDY 24 /* Generated Clocks */
#endif
#endif

326
include/dt-bindings/clock/dra7.h
View File

@@ -16,19 +16,21 @@
#define DRA7_CLKCTRL_OFFSET 0x20
#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* mpu clocks */
#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* ipu clocks */
#define DRA7_IPU_CLKCTRL_OFFSET 0x40
#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
#define _DRA7_IPU_CLKCTRL_OFFSET 0x40
#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80)
/* rtc clocks */
#define DRA7_RTC_CLKCTRL_OFFSET 0x40
@@ -99,65 +101,65 @@
#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
/* l4per clocks */
#define DRA7_L4PER_CLKCTRL_OFFSET 0x0
#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc)
#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14)
#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90)
#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98)
#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4)
#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8)
#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0)
#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8)
#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130)
#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138)
#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160)
#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168)
#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178)
#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190)
#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198)
#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204)
#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208)
#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0
#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc)
#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14)
#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90)
#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98)
#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4)
#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8)
#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0)
#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8)
#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130)
#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138)
#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160)
#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168)
#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170)
#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178)
#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190)
#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198)
#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204)
#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208)
/* wkupaon clocks */
#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
@@ -170,4 +172,192 @@
#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
/* XXX: Compatibility part end. */
/* mpu clocks */
#define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* dsp1 clocks */
#define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* ipu1 clocks */
#define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* ipu clocks */
#define DRA7_IPU_CLKCTRL_OFFSET 0x50
#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
/* dsp2 clocks */
#define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* rtc clocks */
#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
/* coreaon clocks */
#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
/* l3main1 clocks */
#define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
/* ipu2 clocks */
#define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* dma clocks */
#define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* emif clocks */
#define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* atl clocks */
#define DRA7_ATL_CLKCTRL_OFFSET 0x0
#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
#define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
/* l4cfg clocks */
#define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
#define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
#define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
#define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
#define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
#define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
/* l3instr clocks */
#define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* dss clocks */
#define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* l3init clocks */
#define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
#define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
#define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
/* pcie clocks */
#define DRA7_PCIE_CLKCTRL_OFFSET 0xb0
#define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET)
#define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0)
#define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8)
/* gmac clocks */
#define DRA7_GMAC_CLKCTRL_OFFSET 0xd0
#define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET)
#define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0)
/* l4per clocks */
#define DRA7_L4PER_CLKCTRL_OFFSET 0x28
#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
/* l4sec clocks */
#define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0
#define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET)
#define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0)
#define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8)
#define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
#define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
#define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
/* l4per2 clocks */
#define DRA7_L4PER2_CLKCTRL_OFFSET 0xc
#define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET)
#define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc)
#define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18)
#define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20)
#define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90)
#define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98)
#define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4)
#define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138)
#define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160)
#define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168)
#define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178)
#define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190)
#define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198)
#define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0)
#define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0)
#define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8)
#define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0)
#define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204)
#define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208)
/* l4per3 clocks */
#define DRA7_L4PER3_CLKCTRL_OFFSET 0x14
#define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET)
#define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14)
#define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8)
#define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0)
#define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8)
#define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130)
/* wkupaon clocks */
#define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
#define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
#endif

5
include/dt-bindings/clock/exynos3250.h
View File

@@ -1,11 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Tomasz Figa <t.figa@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Samsung Exynos3250 clock controllers.
*/

37
include/dt-bindings/clock/exynos4.h
View File

@@ -1,13 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Exynos4 clock controller.
*/
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
#define _DT_BINDINGS_CLOCK_EXYNOS_4_H
@@ -190,32 +187,6 @@
#define CLK_MIPI_HSI 349 /* Exynos4210 only */
#define CLK_PIXELASYNCM0 351
#define CLK_PIXELASYNCM1 352
#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
#define CLK_PPMUISPX 355 /* Exynos4x12 only */
#define CLK_PPMUISPMX 356 /* Exynos4x12 only */
#define CLK_FIMC_ISP 357 /* Exynos4x12 only */
#define CLK_FIMC_DRC 358 /* Exynos4x12 only */
#define CLK_FIMC_FD 359 /* Exynos4x12 only */
#define CLK_MCUISP 360 /* Exynos4x12 only */
#define CLK_GICISP 361 /* Exynos4x12 only */
#define CLK_SMMU_ISP 362 /* Exynos4x12 only */
#define CLK_SMMU_DRC 363 /* Exynos4x12 only */
#define CLK_SMMU_FD 364 /* Exynos4x12 only */
#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
#define CLK_MPWM_ISP 368 /* Exynos4x12 only */
#define CLK_I2C0_ISP 369 /* Exynos4x12 only */
#define CLK_I2C1_ISP 370 /* Exynos4x12 only */
#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
#define CLK_PWM_ISP 372 /* Exynos4x12 only */
#define CLK_WDT_ISP 373 /* Exynos4x12 only */
#define CLK_UART_ISP 374 /* Exynos4x12 only */
#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
#define CLK_SPI0_ISP 377 /* Exynos4x12 only */
#define CLK_SPI1_ISP 378 /* Exynos4x12 only */
#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
@@ -257,10 +228,6 @@
#define CLK_PPMUACP 415
/* div clocks */
#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
#define CLK_DIV_ISP1 451 /* Exynos4x12 only */
#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
#define CLK_DIV_ACP 456

7
include/dt-bindings/clock/exynos5250.h
View File

@@ -1,13 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Exynos5250 clock controller.
*/
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H

7
include/dt-bindings/clock/exynos5260-clk.h
View File

@@ -1,13 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Rahul Sharma <rahul.sharma@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Provides Constants for Exynos5260 clocks.
*/
*/
#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
#define _DT_BINDINGS_CLK_EXYNOS5260_H

7
include/dt-bindings/clock/exynos5410.h
View File

@@ -1,13 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Copyright (c) 2016 Krzysztof Kozlowski
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Exynos5421 clock controller.
*/
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H

7
include/dt-bindings/clock/exynos5420.h
View File

@@ -1,13 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Exynos5420 clock controller.
*/
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H

5
include/dt-bindings/clock/exynos5433.h
View File

@@ -1,10 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Chanwoo Choi <cw00.choi@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H

7
include/dt-bindings/clock/exynos7-clk.h
View File

@@ -1,11 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
#define _DT_BINDINGS_CLOCK_EXYNOS7_H

348
include/dt-bindings/clock/hi3670-clock.h Normal file
View File

@@ -0,0 +1,348 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Device Tree binding constants for HiSilicon Hi3670 SoC
*
* Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
* Copyright (c) 2018 Linaro Ltd.
*/
#ifndef __DT_BINDINGS_CLOCK_HI3670_H
#define __DT_BINDINGS_CLOCK_HI3670_H
/* clk in stub clock */
#define HI3670_CLK_STUB_CLUSTER0 0
#define HI3670_CLK_STUB_CLUSTER1 1
#define HI3670_CLK_STUB_GPU 2
#define HI3670_CLK_STUB_DDR 3
#define HI3670_CLK_STUB_DDR_VOTE 4
#define HI3670_CLK_STUB_DDR_LIMIT 5
#define HI3670_CLK_STUB_NUM 6
/* clk in crg clock */
#define HI3670_CLKIN_SYS 0
#define HI3670_CLKIN_REF 1
#define HI3670_CLK_FLL_SRC 2
#define HI3670_CLK_PPLL0 3
#define HI3670_CLK_PPLL1 4
#define HI3670_CLK_PPLL2 5
#define HI3670_CLK_PPLL3 6
#define HI3670_CLK_PPLL4 7
#define HI3670_CLK_PPLL6 8
#define HI3670_CLK_PPLL7 9
#define HI3670_CLK_PPLL_PCIE 10
#define HI3670_CLK_PCIEPLL_REV 11
#define HI3670_CLK_SCPLL 12
#define HI3670_PCLK 13
#define HI3670_CLK_UART0_DBG 14
#define HI3670_CLK_UART6 15
#define HI3670_OSC32K 16
#define HI3670_OSC19M 17
#define HI3670_CLK_480M 18
#define HI3670_CLK_INVALID 19
#define HI3670_CLK_DIV_SYSBUS 20
#define HI3670_CLK_FACTOR_MMC 21
#define HI3670_CLK_SD_SYS 22
#define HI3670_CLK_SDIO_SYS 23
#define HI3670_CLK_DIV_A53HPM 24
#define HI3670_CLK_DIV_320M 25
#define HI3670_PCLK_GATE_UART0 26
#define HI3670_CLK_FACTOR_UART0 27
#define HI3670_CLK_FACTOR_USB3PHY_PLL 28
#define HI3670_CLK_GATE_ABB_USB 29
#define HI3670_CLK_GATE_UFSPHY_REF 30
#define HI3670_ICS_VOLT_HIGH 31
#define HI3670_ICS_VOLT_MIDDLE 32
#define HI3670_VENC_VOLT_HOLD 33
#define HI3670_VDEC_VOLT_HOLD 34
#define HI3670_EDC_VOLT_HOLD 35
#define HI3670_CLK_ISP_SNCLK_FAC 36
#define HI3670_CLK_FACTOR_RXDPHY 37
#define HI3670_AUTODIV_SYSBUS 38
#define HI3670_AUTODIV_EMMC0BUS 39
#define HI3670_PCLK_ANDGT_MMC1_PCIE 40
#define HI3670_CLK_GATE_VCODECBUS_GT 41
#define HI3670_CLK_ANDGT_SD 42
#define HI3670_CLK_SD_SYS_GT 43
#define HI3670_CLK_ANDGT_SDIO 44
#define HI3670_CLK_SDIO_SYS_GT 45
#define HI3670_CLK_A53HPM_ANDGT 46
#define HI3670_CLK_320M_PLL_GT 47
#define HI3670_CLK_ANDGT_UARTH 48
#define HI3670_CLK_ANDGT_UARTL 49
#define HI3670_CLK_ANDGT_UART0 50
#define HI3670_CLK_ANDGT_SPI 51
#define HI3670_CLK_ANDGT_PCIEAXI 52
#define HI3670_CLK_DIV_AO_ASP_GT 53
#define HI3670_CLK_GATE_CSI_TRANS 54
#define HI3670_CLK_GATE_DSI_TRANS 55
#define HI3670_CLK_ANDGT_PTP 56
#define HI3670_CLK_ANDGT_OUT0 57
#define HI3670_CLK_ANDGT_OUT1 58
#define HI3670_CLKGT_DP_AUDIO_PLL_AO 59
#define HI3670_CLK_ANDGT_VDEC 60
#define HI3670_CLK_ANDGT_VENC 61
#define HI3670_CLK_ISP_SNCLK_ANGT 62
#define HI3670_CLK_ANDGT_RXDPHY 63
#define HI3670_CLK_ANDGT_ICS 64
#define HI3670_AUTODIV_DMABUS 65
#define HI3670_CLK_MUX_SYSBUS 66
#define HI3670_CLK_MUX_VCODECBUS 67
#define HI3670_CLK_MUX_SD_SYS 68
#define HI3670_CLK_MUX_SD_PLL 69
#define HI3670_CLK_MUX_SDIO_SYS 70
#define HI3670_CLK_MUX_SDIO_PLL 71
#define HI3670_CLK_MUX_A53HPM 72
#define HI3670_CLK_MUX_320M 73
#define HI3670_CLK_MUX_UARTH 74
#define HI3670_CLK_MUX_UARTL 75
#define HI3670_CLK_MUX_UART0 76
#define HI3670_CLK_MUX_I2C 77
#define HI3670_CLK_MUX_SPI 78
#define HI3670_CLK_MUX_PCIEAXI 79
#define HI3670_CLK_MUX_AO_ASP 80
#define HI3670_CLK_MUX_VDEC 81
#define HI3670_CLK_MUX_VENC 82
#define HI3670_CLK_ISP_SNCLK_MUX0 83
#define HI3670_CLK_ISP_SNCLK_MUX1 84
#define HI3670_CLK_ISP_SNCLK_MUX2 85
#define HI3670_CLK_MUX_RXDPHY_CFG 86
#define HI3670_CLK_MUX_ICS 87
#define HI3670_CLK_DIV_CFGBUS 88
#define HI3670_CLK_DIV_MMC0BUS 89
#define HI3670_CLK_DIV_MMC1BUS 90
#define HI3670_PCLK_DIV_MMC1_PCIE 91
#define HI3670_CLK_DIV_VCODECBUS 92
#define HI3670_CLK_DIV_SD 93
#define HI3670_CLK_DIV_SDIO 94
#define HI3670_CLK_DIV_UARTH 95
#define HI3670_CLK_DIV_UARTL 96
#define HI3670_CLK_DIV_UART0 97
#define HI3670_CLK_DIV_I2C 98
#define HI3670_CLK_DIV_SPI 99
#define HI3670_CLK_DIV_PCIEAXI 100
#define HI3670_CLK_DIV_AO_ASP 101
#define HI3670_CLK_DIV_CSI_TRANS 102
#define HI3670_CLK_DIV_DSI_TRANS 103
#define HI3670_CLK_DIV_PTP 104
#define HI3670_CLK_DIV_CLKOUT0_PLL 105
#define HI3670_CLK_DIV_CLKOUT1_PLL 106
#define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107
#define HI3670_CLK_DIV_VDEC 108
#define HI3670_CLK_DIV_VENC 109
#define HI3670_CLK_ISP_SNCLK_DIV0 110
#define HI3670_CLK_ISP_SNCLK_DIV1 111
#define HI3670_CLK_ISP_SNCLK_DIV2 112
#define HI3670_CLK_DIV_ICS 113
#define HI3670_PPLL1_EN_ACPU 114
#define HI3670_PPLL2_EN_ACPU 115
#define HI3670_PPLL3_EN_ACPU 116
#define HI3670_PPLL1_GT_CPU 117
#define HI3670_PPLL2_GT_CPU 118
#define HI3670_PPLL3_GT_CPU 119
#define HI3670_CLK_GATE_PPLL2_MEDIA 120
#define HI3670_CLK_GATE_PPLL3_MEDIA 121
#define HI3670_CLK_GATE_PPLL4_MEDIA 122
#define HI3670_CLK_GATE_PPLL6_MEDIA 123
#define HI3670_CLK_GATE_PPLL7_MEDIA 124
#define HI3670_PCLK_GPIO0 125
#define HI3670_PCLK_GPIO1 126
#define HI3670_PCLK_GPIO2 127
#define HI3670_PCLK_GPIO3 128
#define HI3670_PCLK_GPIO4 129
#define HI3670_PCLK_GPIO5 130
#define HI3670_PCLK_GPIO6 131
#define HI3670_PCLK_GPIO7 132
#define HI3670_PCLK_GPIO8 133
#define HI3670_PCLK_GPIO9 134
#define HI3670_PCLK_GPIO10 135
#define HI3670_PCLK_GPIO11 136
#define HI3670_PCLK_GPIO12 137
#define HI3670_PCLK_GPIO13 138
#define HI3670_PCLK_GPIO14 139
#define HI3670_PCLK_GPIO15 140
#define HI3670_PCLK_GPIO16 141
#define HI3670_PCLK_GPIO17 142
#define HI3670_PCLK_GPIO20 143
#define HI3670_PCLK_GPIO21 144
#define HI3670_PCLK_GATE_DSI0 145
#define HI3670_PCLK_GATE_DSI1 146
#define HI3670_HCLK_GATE_USB3OTG 147
#define HI3670_ACLK_GATE_USB3DVFS 148
#define HI3670_HCLK_GATE_SDIO 149
#define HI3670_PCLK_GATE_PCIE_SYS 150
#define HI3670_PCLK_GATE_PCIE_PHY 151
#define HI3670_PCLK_GATE_MMC1_PCIE 152
#define HI3670_PCLK_GATE_MMC0_IOC 153
#define HI3670_PCLK_GATE_MMC1_IOC 154
#define HI3670_CLK_GATE_DMAC 155
#define HI3670_CLK_GATE_VCODECBUS2DDR 156
#define HI3670_CLK_CCI400_BYPASS 157
#define HI3670_CLK_GATE_CCI400 158
#define HI3670_CLK_GATE_SD 159
#define HI3670_HCLK_GATE_SD 160
#define HI3670_CLK_GATE_SDIO 161
#define HI3670_CLK_GATE_A57HPM 162
#define HI3670_CLK_GATE_A53HPM 163
#define HI3670_CLK_GATE_PA_A53 164
#define HI3670_CLK_GATE_PA_A57 165
#define HI3670_CLK_GATE_PA_G3D 166
#define HI3670_CLK_GATE_GPUHPM 167
#define HI3670_CLK_GATE_PERIHPM 168
#define HI3670_CLK_GATE_AOHPM 169
#define HI3670_CLK_GATE_UART1 170
#define HI3670_CLK_GATE_UART4 171
#define HI3670_PCLK_GATE_UART1 172
#define HI3670_PCLK_GATE_UART4 173
#define HI3670_CLK_GATE_UART2 174
#define HI3670_CLK_GATE_UART5 175
#define HI3670_PCLK_GATE_UART2 176
#define HI3670_PCLK_GATE_UART5 177
#define HI3670_CLK_GATE_UART0 178
#define HI3670_CLK_GATE_I2C3 179
#define HI3670_CLK_GATE_I2C4 180
#define HI3670_CLK_GATE_I2C7 181
#define HI3670_PCLK_GATE_I2C3 182
#define HI3670_PCLK_GATE_I2C4 183
#define HI3670_PCLK_GATE_I2C7 184
#define HI3670_CLK_GATE_SPI1 185
#define HI3670_CLK_GATE_SPI4 186
#define HI3670_PCLK_GATE_SPI1 187
#define HI3670_PCLK_GATE_SPI4 188
#define HI3670_CLK_GATE_USB3OTG_REF 189
#define HI3670_CLK_GATE_USB2PHY_REF 190
#define HI3670_CLK_GATE_PCIEAUX 191
#define HI3670_ACLK_GATE_PCIE 192
#define HI3670_CLK_GATE_MMC1_PCIEAXI 193
#define HI3670_CLK_GATE_PCIEPHY_REF 194
#define HI3670_CLK_GATE_PCIE_DEBOUNCE 195
#define HI3670_CLK_GATE_PCIEIO 196
#define HI3670_CLK_GATE_PCIE_HP 197
#define HI3670_CLK_GATE_AO_ASP 198
#define HI3670_PCLK_GATE_PCTRL 199
#define HI3670_CLK_CSI_TRANS_GT 200
#define HI3670_CLK_DSI_TRANS_GT 201
#define HI3670_CLK_GATE_PWM 202
#define HI3670_ABB_AUDIO_EN0 203
#define HI3670_ABB_AUDIO_EN1 204
#define HI3670_ABB_AUDIO_GT_EN0 205
#define HI3670_ABB_AUDIO_GT_EN1 206
#define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207
#define HI3670_PERI_VOLT_HOLD 208
#define HI3670_PERI_VOLT_MIDDLE 209
#define HI3670_CLK_GATE_ISP_SNCLK0 210
#define HI3670_CLK_GATE_ISP_SNCLK1 211
#define HI3670_CLK_GATE_ISP_SNCLK2 212
#define HI3670_CLK_GATE_RXDPHY0_CFG 213
#define HI3670_CLK_GATE_RXDPHY1_CFG 214
#define HI3670_CLK_GATE_RXDPHY2_CFG 215
#define HI3670_CLK_GATE_TXDPHY0_CFG 216
#define HI3670_CLK_GATE_TXDPHY0_REF 217
#define HI3670_CLK_GATE_TXDPHY1_CFG 218
#define HI3670_CLK_GATE_TXDPHY1_REF 219
#define HI3670_CLK_GATE_MEDIA_TCXO 220
/* clk in sctrl */
#define HI3670_CLK_ANDGT_IOPERI 0
#define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1
#define HI3670_CLK_ANGT_ASP_SUBSYS 2
#define HI3670_CLK_MUX_UFS_SUBSYS 3
#define HI3670_CLK_MUX_CLKOUT0 4
#define HI3670_CLK_MUX_CLKOUT1 5
#define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6
#define HI3670_CLK_MUX_ASP_PLL 7
#define HI3670_CLK_DIV_AOBUS 8
#define HI3670_CLK_DIV_UFS_SUBSYS 9
#define HI3670_CLK_DIV_IOPERI 10
#define HI3670_CLK_DIV_CLKOUT0_TCXO 11
#define HI3670_CLK_DIV_CLKOUT1_TCXO 12
#define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13
#define HI3670_CLK_DIV_ASP_SUBSYS 14
#define HI3670_PPLL0_EN_ACPU 15
#define HI3670_PPLL0_GT_CPU 16
#define HI3670_CLK_GATE_PPLL0_MEDIA 17
#define HI3670_PCLK_GPIO18 18
#define HI3670_PCLK_GPIO19 19
#define HI3670_CLK_GATE_SPI 20
#define HI3670_PCLK_GATE_SPI 21
#define HI3670_CLK_GATE_UFS_SUBSYS 22
#define HI3670_CLK_GATE_UFSIO_REF 23
#define HI3670_PCLK_AO_GPIO0 24
#define HI3670_PCLK_AO_GPIO1 25
#define HI3670_PCLK_AO_GPIO2 26
#define HI3670_PCLK_AO_GPIO3 27
#define HI3670_PCLK_AO_GPIO4 28
#define HI3670_PCLK_AO_GPIO5 29
#define HI3670_PCLK_AO_GPIO6 30
#define HI3670_CLK_GATE_OUT0 31
#define HI3670_CLK_GATE_OUT1 32
#define HI3670_PCLK_GATE_SYSCNT 33
#define HI3670_CLK_GATE_SYSCNT 34
#define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35
#define HI3670_CLK_GATE_ASP_SUBSYS 36
#define HI3670_CLK_GATE_ASP_TCXO 37
#define HI3670_CLK_GATE_DP_AUDIO_PLL 38
/* clk in pmuctrl */
#define HI3670_GATE_ABB_192 0
/* clk in pctrl */
#define HI3670_GATE_UFS_TCXO_EN 0
#define HI3670_GATE_USB_TCXO_EN 1
/* clk in iomcu */
#define HI3670_CLK_GATE_I2C0 0
#define HI3670_CLK_GATE_I2C1 1
#define HI3670_CLK_GATE_I2C2 2
#define HI3670_CLK_GATE_SPI0 3
#define HI3670_CLK_GATE_SPI2 4
#define HI3670_CLK_GATE_UART3 5
#define HI3670_CLK_I2C0_GATE_IOMCU 6
#define HI3670_CLK_I2C1_GATE_IOMCU 7
#define HI3670_CLK_I2C2_GATE_IOMCU 8
#define HI3670_CLK_SPI0_GATE_IOMCU 9
#define HI3670_CLK_SPI2_GATE_IOMCU 10
#define HI3670_CLK_UART3_GATE_IOMCU 11
#define HI3670_CLK_GATE_PERI0_IOMCU 12
/* clk in media1 */
#define HI3670_CLK_GATE_VIVOBUS_ANDGT 0
#define HI3670_CLK_ANDGT_EDC0 1
#define HI3670_CLK_ANDGT_LDI0 2
#define HI3670_CLK_ANDGT_LDI1 3
#define HI3670_CLK_MMBUF_PLL_ANDGT 4
#define HI3670_PCLK_MMBUF_ANDGT 5
#define HI3670_CLK_MUX_VIVOBUS 6
#define HI3670_CLK_MUX_EDC0 7
#define HI3670_CLK_MUX_LDI0 8
#define HI3670_CLK_MUX_LDI1 9
#define HI3670_CLK_SW_MMBUF 10
#define HI3670_CLK_DIV_VIVOBUS 11
#define HI3670_CLK_DIV_EDC0 12
#define HI3670_CLK_DIV_LDI0 13
#define HI3670_CLK_DIV_LDI1 14
#define HI3670_ACLK_DIV_MMBUF 15
#define HI3670_PCLK_DIV_MMBUF 16
#define HI3670_ACLK_GATE_NOC_DSS 17
#define HI3670_PCLK_GATE_NOC_DSS_CFG 18
#define HI3670_PCLK_GATE_MMBUF_CFG 19
#define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20
#define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21
#define HI3670_PCLK_GATE_DSS 22
#define HI3670_ACLK_GATE_DSS 23
#define HI3670_CLK_GATE_VIVOBUSFREQ 24
#define HI3670_CLK_GATE_EDC0 25
#define HI3670_CLK_GATE_LDI0 26
#define HI3670_CLK_GATE_LDI1FREQ 27
#define HI3670_CLK_GATE_BRG 28
#define HI3670_ACLK_GATE_ASC 29
#define HI3670_CLK_GATE_DSS_AXI_MM 30
#define HI3670_CLK_GATE_MMBUF 31
#define HI3670_PCLK_GATE_MMBUF 32
#define HI3670_CLK_GATE_ATDIV_VIVO 33
/* clk in media2 */
#define HI3670_CLK_GATE_VDECFREQ 0
#define HI3670_CLK_GATE_VENCFREQ 1
#define HI3670_CLK_GATE_ICSFREQ 2
#endif /* __DT_BINDINGS_CLOCK_HI3670_H */

3
include/dt-bindings/clock/imx6qdl-clock.h
View File

@@ -273,6 +273,7 @@
#define IMX6QDL_CLK_MLB_PODF 260
#define IMX6QDL_CLK_EPIT1 261
#define IMX6QDL_CLK_EPIT2 262
#define IMX6QDL_CLK_END 263
#define IMX6QDL_CLK_MMDC_P0_IPG 263
#define IMX6QDL_CLK_END 264
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */

4
include/dt-bindings/clock/imx6sl-clock.h
View File

@@ -175,6 +175,8 @@
#define IMX6SL_CLK_SSI2_IPG 162
#define IMX6SL_CLK_SSI3_IPG 163
#define IMX6SL_CLK_SPDIF_GCLK 164
#define IMX6SL_CLK_END 165
#define IMX6SL_CLK_MMDC_P0_IPG 165
#define IMX6SL_CLK_MMDC_P1_IPG 166
#define IMX6SL_CLK_END 167
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */

3
include/dt-bindings/clock/imx6sll-clock.h
View File

@@ -203,7 +203,8 @@
#define IMX6SLL_CLK_GPIO4 176
#define IMX6SLL_CLK_GPIO5 177
#define IMX6SLL_CLK_GPIO6 178
#define IMX6SLL_CLK_MMDC_P1_IPG 179
#define IMX6SLL_CLK_END 179
#define IMX6SLL_CLK_END 180
#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */

3
include/dt-bindings/clock/imx6sx-clock.h
View File

@@ -279,6 +279,7 @@
#define IMX6SX_CLK_LVDS2_OUT 266
#define IMX6SX_CLK_LVDS2_IN 267
#define IMX6SX_CLK_ANACLK2 268
#define IMX6SX_CLK_CLK_END 269
#define IMX6SX_CLK_MMDC_P1_IPG 269
#define IMX6SX_CLK_CLK_END 270
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */

3
include/dt-bindings/clock/imx6ul-clock.h
View File

@@ -259,7 +259,8 @@
#define IMX6UL_CLK_GPIO3 246
#define IMX6UL_CLK_GPIO4 247
#define IMX6UL_CLK_GPIO5 248
#define IMX6UL_CLK_MMDC_P1_IPG 249
#define IMX6UL_CLK_END 249
#define IMX6UL_CLK_END 250
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */

35
include/dt-bindings/clock/jz4725b-cgu.h Normal file
View File

@@ -0,0 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides clock numbers for the ingenic,jz4725b-cgu DT binding.
*/
#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
#define JZ4725B_CLK_EXT 0
#define JZ4725B_CLK_OSC32K 1
#define JZ4725B_CLK_PLL 2
#define JZ4725B_CLK_PLL_HALF 3
#define JZ4725B_CLK_CCLK 4
#define JZ4725B_CLK_HCLK 5
#define JZ4725B_CLK_PCLK 6
#define JZ4725B_CLK_MCLK 7
#define JZ4725B_CLK_IPU 8
#define JZ4725B_CLK_LCD 9
#define JZ4725B_CLK_I2S 10
#define JZ4725B_CLK_SPI 11
#define JZ4725B_CLK_MMC_MUX 12
#define JZ4725B_CLK_UDC 13
#define JZ4725B_CLK_UART 14
#define JZ4725B_CLK_DMA 15
#define JZ4725B_CLK_ADC 16
#define JZ4725B_CLK_I2C 17
#define JZ4725B_CLK_AIC 18
#define JZ4725B_CLK_MMC0 19
#define JZ4725B_CLK_MMC1 20
#define JZ4725B_CLK_BCH 21
#define JZ4725B_CLK_TCU 22
#define JZ4725B_CLK_EXT512 23
#define JZ4725B_CLK_RTC 24
#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */

5
include/dt-bindings/clock/maxim,max77686.h
View File

@@ -1,10 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2014 Google, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clocks for the Maxim 77686 PMIC.
*/

5
include/dt-bindings/clock/maxim,max77802.h
View File

@@ -1,10 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2014 Google, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clocks for the Maxim 77802 PMIC.
*/

116
include/dt-bindings/clock/qcom,camcc-sdm845.h Normal file
View File

@@ -0,0 +1,116 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
/* CAM_CC clock registers */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_AREG_CLK 1
#define CAM_CC_BPS_AXI_CLK 2
#define CAM_CC_BPS_CLK 3
#define CAM_CC_BPS_CLK_SRC 4
#define CAM_CC_CAMNOC_ATB_CLK 5
#define CAM_CC_CAMNOC_AXI_CLK 6
#define CAM_CC_CCI_CLK 7
#define CAM_CC_CCI_CLK_SRC 8
#define CAM_CC_CPAS_AHB_CLK 9
#define CAM_CC_CPHY_RX_CLK_SRC 10
#define CAM_CC_CSI0PHYTIMER_CLK 11
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12
#define CAM_CC_CSI1PHYTIMER_CLK 13
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14
#define CAM_CC_CSI2PHYTIMER_CLK 15
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16
#define CAM_CC_CSI3PHYTIMER_CLK 17
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18
#define CAM_CC_CSIPHY0_CLK 19
#define CAM_CC_CSIPHY1_CLK 20
#define CAM_CC_CSIPHY2_CLK 21
#define CAM_CC_CSIPHY3_CLK 22
#define CAM_CC_FAST_AHB_CLK_SRC 23
#define CAM_CC_FD_CORE_CLK 24
#define CAM_CC_FD_CORE_CLK_SRC 25
#define CAM_CC_FD_CORE_UAR_CLK 26
#define CAM_CC_ICP_APB_CLK 27
#define CAM_CC_ICP_ATB_CLK 28
#define CAM_CC_ICP_CLK 29
#define CAM_CC_ICP_CLK_SRC 30
#define CAM_CC_ICP_CTI_CLK 31
#define CAM_CC_ICP_TS_CLK 32
#define CAM_CC_IFE_0_AXI_CLK 33
#define CAM_CC_IFE_0_CLK 34
#define CAM_CC_IFE_0_CLK_SRC 35
#define CAM_CC_IFE_0_CPHY_RX_CLK 36
#define CAM_CC_IFE_0_CSID_CLK 37
#define CAM_CC_IFE_0_CSID_CLK_SRC 38
#define CAM_CC_IFE_0_DSP_CLK 39
#define CAM_CC_IFE_1_AXI_CLK 40
#define CAM_CC_IFE_1_CLK 41
#define CAM_CC_IFE_1_CLK_SRC 42
#define CAM_CC_IFE_1_CPHY_RX_CLK 43
#define CAM_CC_IFE_1_CSID_CLK 44
#define CAM_CC_IFE_1_CSID_CLK_SRC 45
#define CAM_CC_IFE_1_DSP_CLK 46
#define CAM_CC_IFE_LITE_CLK 47
#define CAM_CC_IFE_LITE_CLK_SRC 48
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49
#define CAM_CC_IFE_LITE_CSID_CLK 50
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51
#define CAM_CC_IPE_0_AHB_CLK 52
#define CAM_CC_IPE_0_AREG_CLK 53
#define CAM_CC_IPE_0_AXI_CLK 54
#define CAM_CC_IPE_0_CLK 55
#define CAM_CC_IPE_0_CLK_SRC 56
#define CAM_CC_IPE_1_AHB_CLK 57
#define CAM_CC_IPE_1_AREG_CLK 58
#define CAM_CC_IPE_1_AXI_CLK 59
#define CAM_CC_IPE_1_CLK 60
#define CAM_CC_IPE_1_CLK_SRC 61
#define CAM_CC_JPEG_CLK 62
#define CAM_CC_JPEG_CLK_SRC 63
#define CAM_CC_LRME_CLK 64
#define CAM_CC_LRME_CLK_SRC 65
#define CAM_CC_MCLK0_CLK 66
#define CAM_CC_MCLK0_CLK_SRC 67
#define CAM_CC_MCLK1_CLK 68
#define CAM_CC_MCLK1_CLK_SRC 69
#define CAM_CC_MCLK2_CLK 70
#define CAM_CC_MCLK2_CLK_SRC 71
#define CAM_CC_MCLK3_CLK 72
#define CAM_CC_MCLK3_CLK_SRC 73
#define CAM_CC_PLL0 74
#define CAM_CC_PLL0_OUT_EVEN 75
#define CAM_CC_PLL1 76
#define CAM_CC_PLL1_OUT_EVEN 77
#define CAM_CC_PLL2 78
#define CAM_CC_PLL2_OUT_EVEN 79
#define CAM_CC_PLL3 80
#define CAM_CC_PLL3_OUT_EVEN 81
#define CAM_CC_SLOW_AHB_CLK_SRC 82
#define CAM_CC_SOC_AHB_CLK 83
#define CAM_CC_SYS_TMR_CLK 84
/* CAM_CC Resets */
#define TITAN_CAM_CC_CCI_BCR 0
#define TITAN_CAM_CC_CPAS_BCR 1
#define TITAN_CAM_CC_CSI0PHY_BCR 2
#define TITAN_CAM_CC_CSI1PHY_BCR 3
#define TITAN_CAM_CC_CSI2PHY_BCR 4
#define TITAN_CAM_CC_MCLK0_BCR 5
#define TITAN_CAM_CC_MCLK1_BCR 6
#define TITAN_CAM_CC_MCLK2_BCR 7
#define TITAN_CAM_CC_MCLK3_BCR 8
#define TITAN_CAM_CC_TITAN_TOP_BCR 9
/* CAM_CC GDSCRs */
#define BPS_GDSC 0
#define IPE_0_GDSC 1
#define IPE_1_GDSC 2
#define IFE_0_GDSC 3
#define IFE_1_GDSC 4
#define TITAN_TOP_GDSC 5
#endif

2
include/dt-bindings/clock/qcom,gcc-msm8960.h
View File

@@ -319,5 +319,7 @@
#define CE3_SRC 303
#define CE3_CORE_CLK 304
#define CE3_H_CLK 305
#define PLL16 306
#define PLL17 307
#endif

9
include/dt-bindings/clock/qcom,gcc-msm8996.h
View File

@@ -235,6 +235,15 @@
#define GCC_RX1_USB2_CLKREF_CLK 218
#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219
#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220
#define GCC_EDP_CLKREF_CLK 221
#define GCC_MSS_CFG_AHB_CLK 222
#define GCC_MSS_Q6_BIMC_AXI_CLK 223
#define GCC_MSS_SNOC_AXI_CLK 224
#define GCC_MSS_MNOC_BIMC_AXI_CLK 225
#define GCC_DCC_AHB_CLK 226
#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227
#define GCC_MMSS_GPLL0_DIV_CLK 228
#define GCC_MSS_GPLL0_DIV_CLK 229
#define GCC_SYSTEM_NOC_BCR 0
#define GCC_CONFIG_NOC_BCR 1

165
include/dt-bindings/clock/qcom,gcc-qcs404.h Normal file
View File

@@ -0,0 +1,165 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
#define GCC_APSS_AHB_CLK_SRC 0
#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1
#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2
#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3
#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4
#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5
#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6
#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7
#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8
#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9
#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10
#define GCC_BLSP1_UART0_APPS_CLK_SRC 11
#define GCC_BLSP1_UART1_APPS_CLK_SRC 12
#define GCC_BLSP1_UART2_APPS_CLK_SRC 13
#define GCC_BLSP1_UART3_APPS_CLK_SRC 14
#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15
#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16
#define GCC_BLSP2_UART0_APPS_CLK_SRC 17
#define GCC_BYTE0_CLK_SRC 18
#define GCC_EMAC_CLK_SRC 19
#define GCC_EMAC_PTP_CLK_SRC 20
#define GCC_ESC0_CLK_SRC 21
#define GCC_APSS_AHB_CLK 22
#define GCC_APSS_AXI_CLK 23
#define GCC_BIMC_APSS_AXI_CLK 24
#define GCC_BIMC_GFX_CLK 25
#define GCC_BIMC_MDSS_CLK 26
#define GCC_BLSP1_AHB_CLK 27
#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28
#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37
#define GCC_BLSP1_UART0_APPS_CLK 38
#define GCC_BLSP1_UART1_APPS_CLK 39
#define GCC_BLSP1_UART2_APPS_CLK 40
#define GCC_BLSP1_UART3_APPS_CLK 41
#define GCC_BLSP2_AHB_CLK 42
#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43
#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44
#define GCC_BLSP2_UART0_APPS_CLK 45
#define GCC_BOOT_ROM_AHB_CLK 46
#define GCC_DCC_CLK 47
#define GCC_GENI_IR_H_CLK 48
#define GCC_ETH_AXI_CLK 49
#define GCC_ETH_PTP_CLK 50
#define GCC_ETH_RGMII_CLK 51
#define GCC_ETH_SLAVE_AHB_CLK 52
#define GCC_GENI_IR_S_CLK 53
#define GCC_GP1_CLK 54
#define GCC_GP2_CLK 55
#define GCC_GP3_CLK 56
#define GCC_MDSS_AHB_CLK 57
#define GCC_MDSS_AXI_CLK 58
#define GCC_MDSS_BYTE0_CLK 59
#define GCC_MDSS_ESC0_CLK 60
#define GCC_MDSS_HDMI_APP_CLK 61
#define GCC_MDSS_HDMI_PCLK_CLK 62
#define GCC_MDSS_MDP_CLK 63
#define GCC_MDSS_PCLK0_CLK 64
#define GCC_MDSS_VSYNC_CLK 65
#define GCC_OXILI_AHB_CLK 66
#define GCC_OXILI_GFX3D_CLK 67
#define GCC_PCIE_0_AUX_CLK 68
#define GCC_PCIE_0_CFG_AHB_CLK 69
#define GCC_PCIE_0_MSTR_AXI_CLK 70
#define GCC_PCIE_0_PIPE_CLK 71
#define GCC_PCIE_0_SLV_AXI_CLK 72
#define GCC_PCNOC_USB2_CLK 73
#define GCC_PCNOC_USB3_CLK 74
#define GCC_PDM2_CLK 75
#define GCC_PDM_AHB_CLK 76
#define GCC_VSYNC_CLK_SRC 77
#define GCC_PRNG_AHB_CLK 78
#define GCC_PWM0_XO512_CLK 79
#define GCC_PWM1_XO512_CLK 80
#define GCC_PWM2_XO512_CLK 81
#define GCC_SDCC1_AHB_CLK 82
#define GCC_SDCC1_APPS_CLK 83
#define GCC_SDCC1_ICE_CORE_CLK 84
#define GCC_SDCC2_AHB_CLK 85
#define GCC_SDCC2_APPS_CLK 86
#define GCC_SYS_NOC_USB3_CLK 87
#define GCC_USB20_MOCK_UTMI_CLK 88
#define GCC_USB2A_PHY_SLEEP_CLK 89
#define GCC_USB30_MASTER_CLK 90
#define GCC_USB30_MOCK_UTMI_CLK 91
#define GCC_USB30_SLEEP_CLK 92
#define GCC_USB3_PHY_AUX_CLK 93
#define GCC_USB3_PHY_PIPE_CLK 94
#define GCC_USB_HS_PHY_CFG_AHB_CLK 95
#define GCC_USB_HS_SYSTEM_CLK 96
#define GCC_GFX3D_CLK_SRC 97
#define GCC_GP1_CLK_SRC 98
#define GCC_GP2_CLK_SRC 99
#define GCC_GP3_CLK_SRC 100
#define GCC_GPLL0_OUT_MAIN 101
#define GCC_GPLL1_OUT_MAIN 102
#define GCC_GPLL3_OUT_MAIN 103
#define GCC_GPLL4_OUT_MAIN 104
#define GCC_HDMI_APP_CLK_SRC 105
#define GCC_HDMI_PCLK_CLK_SRC 106
#define GCC_MDP_CLK_SRC 107
#define GCC_PCIE_0_AUX_CLK_SRC 108
#define GCC_PCIE_0_PIPE_CLK_SRC 109
#define GCC_PCLK0_CLK_SRC 110
#define GCC_PDM2_CLK_SRC 111
#define GCC_SDCC1_APPS_CLK_SRC 112
#define GCC_SDCC1_ICE_CORE_CLK_SRC 113
#define GCC_SDCC2_APPS_CLK_SRC 114
#define GCC_USB20_MOCK_UTMI_CLK_SRC 115
#define GCC_USB30_MASTER_CLK_SRC 116
#define GCC_USB30_MOCK_UTMI_CLK_SRC 117
#define GCC_USB3_PHY_AUX_CLK_SRC 118
#define GCC_USB_HS_SYSTEM_CLK_SRC 119
#define GCC_GPLL0_AO_CLK_SRC 120
#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122
#define GCC_GPLL0_AO_OUT_MAIN 123
#define GCC_GPLL0_SLEEP_CLK_SRC 124
#define GCC_GPLL6 125
#define GCC_GPLL6_OUT_AUX 126
#define GCC_MDSS_MDP_VOTE_CLK 127
#define GCC_MDSS_ROTATOR_VOTE_CLK 128
#define GCC_BIMC_GPU_CLK 129
#define GCC_GTCU_AHB_CLK 130
#define GCC_GFX_TCU_CLK 131
#define GCC_GFX_TBU_CLK 132
#define GCC_SMMU_CFG_CLK 133
#define GCC_APSS_TCU_CLK 134
#define GCC_CRYPTO_AHB_CLK 135
#define GCC_CRYPTO_AXI_CLK 136
#define GCC_CRYPTO_CLK 137
#define GCC_MDP_TBU_CLK 138
#define GCC_QDSS_DAP_CLK 139
#define GCC_DCC_XO_CLK 140
#define GCC_GENI_IR_BCR 0
#define GCC_USB_HS_BCR 1
#define GCC_USB2_HS_PHY_ONLY_BCR 2
#define GCC_QUSB2_PHY_BCR 3
#define GCC_USB_HS_PHY_CFG_AHB_BCR 4
#define GCC_USB2A_PHY_BCR 5
#define GCC_USB3_PHY_BCR 6
#define GCC_USB_30_BCR 7
#define GCC_USB3PHY_PHY_BCR 8
#define GCC_PCIE_0_BCR 9
#define GCC_PCIE_0_PHY_BCR 10
#define GCC_PCIE_0_LINK_DOWN_BCR 11
#define GCC_PCIEPHY_0_PHY_BCR 12
#define GCC_EMAC_BCR 13
#endif

156
include/dt-bindings/clock/qcom,gcc-sdm660.h Normal file
View File

@@ -0,0 +1,156 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
* Copyright (c) 2018, Craig Tatlor.
*/
#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
#define _DT_BINDINGS_CLK_MSM_GCC_660_H
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
#define BLSP1_UART1_APPS_CLK_SRC 8
#define BLSP1_UART2_APPS_CLK_SRC 9
#define BLSP2_QUP1_I2C_APPS_CLK_SRC 10
#define BLSP2_QUP1_SPI_APPS_CLK_SRC 11
#define BLSP2_QUP2_I2C_APPS_CLK_SRC 12
#define BLSP2_QUP2_SPI_APPS_CLK_SRC 13
#define BLSP2_QUP3_I2C_APPS_CLK_SRC 14
#define BLSP2_QUP3_SPI_APPS_CLK_SRC 15
#define BLSP2_QUP4_I2C_APPS_CLK_SRC 16
#define BLSP2_QUP4_SPI_APPS_CLK_SRC 17
#define BLSP2_UART1_APPS_CLK_SRC 18
#define BLSP2_UART2_APPS_CLK_SRC 19
#define GCC_AGGRE2_UFS_AXI_CLK 20
#define GCC_AGGRE2_USB3_AXI_CLK 21
#define GCC_BIMC_GFX_CLK 22
#define GCC_BIMC_HMSS_AXI_CLK 23
#define GCC_BIMC_MSS_Q6_AXI_CLK 24
#define GCC_BLSP1_AHB_CLK 25
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 26
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 27
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 28
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 29
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 30
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 31
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 32
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 33
#define GCC_BLSP1_UART1_APPS_CLK 34
#define GCC_BLSP1_UART2_APPS_CLK 35
#define GCC_BLSP2_AHB_CLK 36
#define GCC_BLSP2_QUP1_I2C_APPS_CLK 37
#define GCC_BLSP2_QUP1_SPI_APPS_CLK 38
#define GCC_BLSP2_QUP2_I2C_APPS_CLK 39
#define GCC_BLSP2_QUP2_SPI_APPS_CLK 40
#define GCC_BLSP2_QUP3_I2C_APPS_CLK 41
#define GCC_BLSP2_QUP3_SPI_APPS_CLK 42
#define GCC_BLSP2_QUP4_I2C_APPS_CLK 43
#define GCC_BLSP2_QUP4_SPI_APPS_CLK 44
#define GCC_BLSP2_UART1_APPS_CLK 45
#define GCC_BLSP2_UART2_APPS_CLK 46
#define GCC_BOOT_ROM_AHB_CLK 47
#define GCC_CFG_NOC_USB2_AXI_CLK 48
#define GCC_CFG_NOC_USB3_AXI_CLK 49
#define GCC_DCC_AHB_CLK 50
#define GCC_GP1_CLK 51
#define GCC_GP2_CLK 52
#define GCC_GP3_CLK 53
#define GCC_GPU_BIMC_GFX_CLK 54
#define GCC_GPU_CFG_AHB_CLK 55
#define GCC_GPU_GPLL0_CLK 56
#define GCC_GPU_GPLL0_DIV_CLK 57
#define GCC_HMSS_DVM_BUS_CLK 58
#define GCC_HMSS_RBCPR_CLK 59
#define GCC_MMSS_GPLL0_CLK 60
#define GCC_MMSS_GPLL0_DIV_CLK 61
#define GCC_MMSS_NOC_CFG_AHB_CLK 62
#define GCC_MMSS_SYS_NOC_AXI_CLK 63
#define GCC_MSS_CFG_AHB_CLK 64
#define GCC_MSS_GPLL0_DIV_CLK 65
#define GCC_MSS_MNOC_BIMC_AXI_CLK 66
#define GCC_MSS_Q6_BIMC_AXI_CLK 67
#define GCC_MSS_SNOC_AXI_CLK 68
#define GCC_PDM2_CLK 69
#define GCC_PDM_AHB_CLK 70
#define GCC_PRNG_AHB_CLK 71
#define GCC_QSPI_AHB_CLK 72
#define GCC_QSPI_SER_CLK 73
#define GCC_SDCC1_AHB_CLK 74
#define GCC_SDCC1_APPS_CLK 75
#define GCC_SDCC1_ICE_CORE_CLK 76
#define GCC_SDCC2_AHB_CLK 77
#define GCC_SDCC2_APPS_CLK 78
#define GCC_UFS_AHB_CLK 79
#define GCC_UFS_AXI_CLK 80
#define GCC_UFS_CLKREF_CLK 81
#define GCC_UFS_ICE_CORE_CLK 82
#define GCC_UFS_PHY_AUX_CLK 83
#define GCC_UFS_RX_SYMBOL_0_CLK 84
#define GCC_UFS_RX_SYMBOL_1_CLK 85
#define GCC_UFS_TX_SYMBOL_0_CLK 86
#define GCC_UFS_UNIPRO_CORE_CLK 87
#define GCC_USB20_MASTER_CLK 88
#define GCC_USB20_MOCK_UTMI_CLK 89
#define GCC_USB20_SLEEP_CLK 90
#define GCC_USB30_MASTER_CLK 91
#define GCC_USB30_MOCK_UTMI_CLK 92
#define GCC_USB30_SLEEP_CLK 93
#define GCC_USB3_CLKREF_CLK 94
#define GCC_USB3_PHY_AUX_CLK 95
#define GCC_USB3_PHY_PIPE_CLK 96
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 97
#define GP1_CLK_SRC 98
#define GP2_CLK_SRC 99
#define GP3_CLK_SRC 100
#define GPLL0 101
#define GPLL0_EARLY 102
#define GPLL1 103
#define GPLL1_EARLY 104
#define GPLL4 105
#define GPLL4_EARLY 106
#define HMSS_GPLL0_CLK_SRC 107
#define HMSS_GPLL4_CLK_SRC 108
#define HMSS_RBCPR_CLK_SRC 109
#define PDM2_CLK_SRC 110
#define QSPI_SER_CLK_SRC 111
#define SDCC1_APPS_CLK_SRC 112
#define SDCC1_ICE_CORE_CLK_SRC 113
#define SDCC2_APPS_CLK_SRC 114
#define UFS_AXI_CLK_SRC 115
#define UFS_ICE_CORE_CLK_SRC 116
#define UFS_PHY_AUX_CLK_SRC 117
#define UFS_UNIPRO_CORE_CLK_SRC 118
#define USB20_MASTER_CLK_SRC 119
#define USB20_MOCK_UTMI_CLK_SRC 120
#define USB30_MASTER_CLK_SRC 121
#define USB30_MOCK_UTMI_CLK_SRC 122
#define USB3_PHY_AUX_CLK_SRC 123
#define GPLL0_OUT_MSSCC 124
#define GCC_UFS_AXI_HW_CTL_CLK 125
#define GCC_UFS_ICE_CORE_HW_CTL_CLK 126
#define GCC_UFS_PHY_AUX_HW_CTL_CLK 127
#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128
#define GCC_RX0_USB2_CLKREF_CLK 129
#define GCC_RX1_USB2_CLKREF_CLK 130
#define PCIE_0_GDSC 0
#define UFS_GDSC 1
#define USB_30_GDSC 2
#define GCC_QUSB2PHY_PRIM_BCR 0
#define GCC_QUSB2PHY_SEC_BCR 1
#define GCC_UFS_BCR 2
#define GCC_USB3_DP_PHY_BCR 3
#define GCC_USB3_PHY_BCR 4
#define GCC_USB3PHY_PHY_BCR 5
#define GCC_USB_20_BCR 6
#define GCC_USB_30_BCR 7
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
#endif

3
include/dt-bindings/clock/qcom,gcc-sdm845.h
View File

@@ -194,6 +194,9 @@
#define GPLL4 184
#define GCC_CPUSS_DVM_BUS_CLK 185
#define GCC_CPUSS_GNOC_CLK 186
#define GCC_QSPI_CORE_CLK_SRC 187
#define GCC_QSPI_CORE_CLK 188
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
/* GCC Resets */
#define GCC_MMSS_BCR 0

7
include/dt-bindings/clock/r7s72100-clock.h
View File

@@ -1,10 +1,7 @@
/*
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2014 Renesas Solutions Corp.
* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__

20
include/dt-bindings/clock/r7s9210-cpg-mssr.h Normal file
View File

@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*
*/
#ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R7S9210 CPG Core Clocks */
#define R7S9210_CLK_I 0
#define R7S9210_CLK_G 1
#define R7S9210_CLK_B 2
#define R7S9210_CLK_P1 3
#define R7S9210_CLK_P1C 4
#define R7S9210_CLK_P0 5
#endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */

8
include/dt-bindings/clock/r8a7743-cpg-mssr.h
View File

@@ -1,10 +1,6 @@
/*
* Copyright (C) 2016 Cogent Embedded Inc.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2016 Cogent Embedded Inc.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__

39
include/dt-bindings/clock/r8a7744-cpg-mssr.h Normal file
View File

@@ -0,0 +1,39 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7744 CPG Core Clocks */
#define R8A7744_CLK_Z 0
#define R8A7744_CLK_ZG 1
#define R8A7744_CLK_ZTR 2
#define R8A7744_CLK_ZTRD2 3
#define R8A7744_CLK_ZT 4
#define R8A7744_CLK_ZX 5
#define R8A7744_CLK_ZS 6
#define R8A7744_CLK_HP 7
#define R8A7744_CLK_B 9
#define R8A7744_CLK_LB 10
#define R8A7744_CLK_P 11
#define R8A7744_CLK_CL 12
#define R8A7744_CLK_M2 13
#define R8A7744_CLK_ZB3 15
#define R8A7744_CLK_ZB3D2 16
#define R8A7744_CLK_DDR 17
#define R8A7744_CLK_SDH 18
#define R8A7744_CLK_SD0 19
#define R8A7744_CLK_SD2 20
#define R8A7744_CLK_SD3 21
#define R8A7744_CLK_MMC0 22
#define R8A7744_CLK_MP 23
#define R8A7744_CLK_QSPI 26
#define R8A7744_CLK_CP 27
#define R8A7744_CLK_RCAN 28
#define R8A7744_CLK_R 29
#define R8A7744_CLK_OSC 30
#endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */

8
include/dt-bindings/clock/r8a7745-cpg-mssr.h
View File

@@ -1,10 +1,6 @@
/*
* Copyright (C) 2016 Cogent Embedded Inc.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2016 Cogent Embedded Inc.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__

58
include/dt-bindings/clock/r8a774a1-cpg-mssr.h Normal file
View File

@@ -0,0 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a774a1 CPG Core Clocks */
#define R8A774A1_CLK_Z 0
#define R8A774A1_CLK_Z2 1
#define R8A774A1_CLK_ZG 2
#define R8A774A1_CLK_ZTR 3
#define R8A774A1_CLK_ZTRD2 4
#define R8A774A1_CLK_ZT 5
#define R8A774A1_CLK_ZX 6
#define R8A774A1_CLK_S0D1 7
#define R8A774A1_CLK_S0D2 8
#define R8A774A1_CLK_S0D3 9
#define R8A774A1_CLK_S0D4 10
#define R8A774A1_CLK_S0D6 11
#define R8A774A1_CLK_S0D8 12
#define R8A774A1_CLK_S0D12 13
#define R8A774A1_CLK_S1D2 14
#define R8A774A1_CLK_S1D4 15
#define R8A774A1_CLK_S2D1 16
#define R8A774A1_CLK_S2D2 17
#define R8A774A1_CLK_S2D4 18
#define R8A774A1_CLK_S3D1 19
#define R8A774A1_CLK_S3D2 20
#define R8A774A1_CLK_S3D4 21
#define R8A774A1_CLK_LB 22
#define R8A774A1_CLK_CL 23
#define R8A774A1_CLK_ZB3 24
#define R8A774A1_CLK_ZB3D2 25
#define R8A774A1_CLK_ZB3D4 26
#define R8A774A1_CLK_CR 27
#define R8A774A1_CLK_CRD2 28
#define R8A774A1_CLK_SD0H 29
#define R8A774A1_CLK_SD0 30
#define R8A774A1_CLK_SD1H 31
#define R8A774A1_CLK_SD1 32
#define R8A774A1_CLK_SD2H 33
#define R8A774A1_CLK_SD2 34
#define R8A774A1_CLK_SD3H 35
#define R8A774A1_CLK_SD3 36
#define R8A774A1_CLK_RPC 37
#define R8A774A1_CLK_RPCD2 38
#define R8A774A1_CLK_MSO 39
#define R8A774A1_CLK_HDMI 40
#define R8A774A1_CLK_CSI0 41
#define R8A774A1_CLK_CP 42
#define R8A774A1_CLK_CPEX 43
#define R8A774A1_CLK_R 44
#define R8A774A1_CLK_OSC 45
#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */

60
include/dt-bindings/clock/r8a774c0-cpg-mssr.h Normal file
View File

@@ -0,0 +1,60 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a774c0 CPG Core Clocks */
#define R8A774C0_CLK_Z2 0
#define R8A774C0_CLK_ZG 1
#define R8A774C0_CLK_ZTR 2
#define R8A774C0_CLK_ZT 3
#define R8A774C0_CLK_ZX 4
#define R8A774C0_CLK_S0D1 5
#define R8A774C0_CLK_S0D3 6
#define R8A774C0_CLK_S0D6 7
#define R8A774C0_CLK_S0D12 8
#define R8A774C0_CLK_S0D24 9
#define R8A774C0_CLK_S1D1 10
#define R8A774C0_CLK_S1D2 11
#define R8A774C0_CLK_S1D4 12
#define R8A774C0_CLK_S2D1 13
#define R8A774C0_CLK_S2D2 14
#define R8A774C0_CLK_S2D4 15
#define R8A774C0_CLK_S3D1 16
#define R8A774C0_CLK_S3D2 17
#define R8A774C0_CLK_S3D4 18
#define R8A774C0_CLK_S0D6C 19
#define R8A774C0_CLK_S3D1C 20
#define R8A774C0_CLK_S3D2C 21
#define R8A774C0_CLK_S3D4C 22
#define R8A774C0_CLK_LB 23
#define R8A774C0_CLK_CL 24
#define R8A774C0_CLK_ZB3 25
#define R8A774C0_CLK_ZB3D2 26
#define R8A774C0_CLK_CR 27
#define R8A774C0_CLK_CRD2 28
#define R8A774C0_CLK_SD0H 29
#define R8A774C0_CLK_SD0 30
#define R8A774C0_CLK_SD1H 31
#define R8A774C0_CLK_SD1 32
#define R8A774C0_CLK_SD3H 33
#define R8A774C0_CLK_SD3 34
#define R8A774C0_CLK_RPC 35
#define R8A774C0_CLK_RPCD2 36
#define R8A774C0_CLK_ZA2 37
#define R8A774C0_CLK_ZA8 38
#define R8A774C0_CLK_Z2D 39
#define R8A774C0_CLK_MSO 40
#define R8A774C0_CLK_R 41
#define R8A774C0_CLK_OSC 42
#define R8A774C0_CLK_LV0 43
#define R8A774C0_CLK_LV1 44
#define R8A774C0_CLK_CSI0 45
#define R8A774C0_CLK_CP 46
#define R8A774C0_CLK_CPEX 47
#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */

8
include/dt-bindings/clock/r8a7790-cpg-mssr.h
View File

@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a7791-cpg-mssr.h
View File

@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a7792-cpg-mssr.h
View File

@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__

12
include/dt-bindings/clock/r8a7793-clock.h
View File

@@ -1,16 +1,8 @@
/*
/* SPDX-License-Identifier: GPL-2.0
*
* r8a7793 clock definition
*
* Copyright (C) 2014 Renesas Electronics Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__

8
include/dt-bindings/clock/r8a7793-cpg-mssr.h
View File

@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a7794-clock.h
View File

@@ -1,11 +1,7 @@
/*
/* SPDX-License-Identifier: GPL-2.0+
*
* Copyright (C) 2014 Renesas Electronics Corporation
* Copyright 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__

8
include/dt-bindings/clock/r8a7794-cpg-mssr.h
View File

@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a7795-cpg-mssr.h
View File

@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a7796-cpg-mssr.h
View File

@@ -1,10 +1,6 @@
/*
* Copyright (C) 2016 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2016 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a77970-cpg-mssr.h
View File

@@ -1,11 +1,7 @@
/*
/* SPDX-License-Identifier: GPL-2.0+
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__

8
include/dt-bindings/clock/r8a77995-cpg-mssr.h
View File

@@ -1,10 +1,6 @@
/*
* Copyright (C) 2017 Glider bvba
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2017 Glider bvba
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__

8
include/dt-bindings/clock/renesas-cpg-mssr.h
View File

@@ -1,10 +1,6 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
/* SPDX-License-Identifier: GPL-2.0+
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__

3
include/dt-bindings/clock/rk3188-cru-common.h
View File

@@ -139,8 +139,9 @@
#define HCLK_CIF1 470
#define HCLK_VEPU 471
#define HCLK_VDPU 472
#define HCLK_HDMI 473
#define CLK_NR_CLKS (HCLK_VDPU + 1)
#define CLK_NR_CLKS (HCLK_HDMI + 1)
/* soft-reset indices */
#define SRST_MCORE 2

5
include/dt-bindings/clock/s3c2410.h
View File

@@ -1,10 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clock controllers of Samsung S3C2410 and later.
*/

5
include/dt-bindings/clock/s3c2412.h
View File

@@ -1,10 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clock controllers of Samsung S3C2412.
*/

5
include/dt-bindings/clock/s3c2443.h
View File

@@ -1,10 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clock controllers of Samsung S3C2443 and later.
*/

5
include/dt-bindings/clock/samsung,s2mps11.h
View File

@@ -1,10 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2015 Markus Reichl
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clocks for the Samsung S2MPS11 PMIC.
*/

7
include/dt-bindings/clock/samsung,s3c64xx-clock.h
View File

@@ -1,12 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Samsung S3C64xx clock controller.
*/
*/
#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H

1
include/dt-bindings/clock/sun50i-a64-ccu.h
View File

@@ -43,6 +43,7 @@
#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
#define _DT_BINDINGS_CLK_SUN50I_A64_H_
#define CLK_PLL_VIDEO0 7
#define CLK_PLL_PERIPH0 11
#define CLK_BUS_MIPI_DSI 28

116
include/dt-bindings/clock/xlnx,zynqmp-clk.h Normal file
View File

@@ -0,0 +1,116 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Xilinx Zynq MPSoC Firmware layer
*
* Copyright (C) 2014-2018 Xilinx, Inc.
*
*/
#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
#define _DT_BINDINGS_CLK_ZYNQMP_H
#define IOPLL 0
#define RPLL 1
#define APLL 2
#define DPLL 3
#define VPLL 4
#define IOPLL_TO_FPD 5
#define RPLL_TO_FPD 6
#define APLL_TO_LPD 7
#define DPLL_TO_LPD 8
#define VPLL_TO_LPD 9
#define ACPU 10
#define ACPU_HALF 11
#define DBF_FPD 12
#define DBF_LPD 13
#define DBG_TRACE 14
#define DBG_TSTMP 15
#define DP_VIDEO_REF 16
#define DP_AUDIO_REF 17
#define DP_STC_REF 18
#define GDMA_REF 19
#define DPDMA_REF 20
#define DDR_REF 21
#define SATA_REF 22
#define PCIE_REF 23
#define GPU_REF 24
#define GPU_PP0_REF 25
#define GPU_PP1_REF 26
#define TOPSW_MAIN 27
#define TOPSW_LSBUS 28
#define GTGREF0_REF 29
#define LPD_SWITCH 30
#define LPD_LSBUS 31
#define USB0_BUS_REF 32
#define USB1_BUS_REF 33
#define USB3_DUAL_REF 34
#define USB0 35
#define USB1 36
#define CPU_R5 37
#define CPU_R5_CORE 38
#define CSU_SPB 39
#define CSU_PLL 40
#define PCAP 41
#define IOU_SWITCH 42
#define GEM_TSU_REF 43
#define GEM_TSU 44
#define GEM0_REF 45
#define GEM1_REF 46
#define GEM2_REF 47
#define GEM3_REF 48
#define GEM0_TX 49
#define GEM1_TX 50
#define GEM2_TX 51
#define GEM3_TX 52
#define QSPI_REF 53
#define SDIO0_REF 54
#define SDIO1_REF 55
#define UART0_REF 56
#define UART1_REF 57
#define SPI0_REF 58
#define SPI1_REF 59
#define NAND_REF 60
#define I2C0_REF 61
#define I2C1_REF 62
#define CAN0_REF 63
#define CAN1_REF 64
#define CAN0 65
#define CAN1 66
#define DLL_REF 67
#define ADMA_REF 68
#define TIMESTAMP_REF 69
#define AMS_REF 70
#define PL0_REF 71
#define PL1_REF 72
#define PL2_REF 73
#define PL3_REF 74
#define WDT 75
#define IOPLL_INT 76
#define IOPLL_PRE_SRC 77
#define IOPLL_HALF 78
#define IOPLL_INT_MUX 79
#define IOPLL_POST_SRC 80
#define RPLL_INT 81
#define RPLL_PRE_SRC 82
#define RPLL_HALF 83
#define RPLL_INT_MUX 84
#define RPLL_POST_SRC 85
#define APLL_INT 86
#define APLL_PRE_SRC 87
#define APLL_HALF 88
#define APLL_INT_MUX 89
#define APLL_POST_SRC 90
#define DPLL_INT 91
#define DPLL_PRE_SRC 92
#define DPLL_HALF 93
#define DPLL_INT_MUX 94
#define DPLL_POST_SRC 95
#define VPLL_INT 96
#define VPLL_PRE_SRC 97
#define VPLL_HALF 98
#define VPLL_INT_MUX 99
#define VPLL_POST_SRC 100
#define CAN0_MIO 101
#define CAN1_MIO 102
#endif

114
include/dt-bindings/gpio/meson-g12a-gpio.h Normal file
View File

@@ -0,0 +1,114 @@
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
/*
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
*/
#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
#define _DT_BINDINGS_MESON_G12A_GPIO_H
/* First GPIO chip */
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOE_0 12
#define GPIOE_1 13
#define GPIOE_2 14
/* Second GPIO chip */
#define GPIOZ_0 0
#define GPIOZ_1 1
#define GPIOZ_2 2
#define GPIOZ_3 3
#define GPIOZ_4 4
#define GPIOZ_5 5
#define GPIOZ_6 6
#define GPIOZ_7 7
#define GPIOZ_8 8
#define GPIOZ_9 9
#define GPIOZ_10 10
#define GPIOZ_11 11
#define GPIOZ_12 12
#define GPIOZ_13 13
#define GPIOZ_14 14
#define GPIOZ_15 15
#define GPIOH_0 16
#define GPIOH_1 17
#define GPIOH_2 18
#define GPIOH_3 19
#define GPIOH_4 20
#define GPIOH_5 21
#define GPIOH_6 22
#define GPIOH_7 23
#define GPIOH_8 24
#define BOOT_0 25
#define BOOT_1 26
#define BOOT_2 27
#define BOOT_3 28
#define BOOT_4 29
#define BOOT_5 30
#define BOOT_6 31
#define BOOT_7 32
#define BOOT_8 33
#define BOOT_9 34
#define BOOT_10 35
#define BOOT_11 36
#define BOOT_12 37
#define BOOT_13 38
#define BOOT_14 39
#define BOOT_15 40
#define GPIOC_0 41
#define GPIOC_1 42
#define GPIOC_2 43
#define GPIOC_3 44
#define GPIOC_4 45
#define GPIOC_5 46
#define GPIOC_6 47
#define GPIOC_7 48
#define GPIOA_0 49
#define GPIOA_1 50
#define GPIOA_2 51
#define GPIOA_3 52
#define GPIOA_4 53
#define GPIOA_5 54
#define GPIOA_6 55
#define GPIOA_7 56
#define GPIOA_8 57
#define GPIOA_9 58
#define GPIOA_10 59
#define GPIOA_11 60
#define GPIOA_12 61
#define GPIOA_13 62
#define GPIOA_14 63
#define GPIOA_15 64
#define GPIOX_0 65
#define GPIOX_1 66
#define GPIOX_2 67
#define GPIOX_3 68
#define GPIOX_4 69
#define GPIOX_5 70
#define GPIOX_6 71
#define GPIOX_7 72
#define GPIOX_8 73
#define GPIOX_9 74
#define GPIOX_10 75
#define GPIOX_11 76
#define GPIOX_12 77
#define GPIOX_13 78
#define GPIOX_14 79
#define GPIOX_15 80
#define GPIOX_16 81
#define GPIOX_17 82
#define GPIOX_18 83
#define GPIOX_19 84
#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */

125
include/dt-bindings/iio/qcom,spmi-vadc.h
View File

@@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* Copyright (c) 2012-2014,2018 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
@@ -116,4 +108,117 @@
#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9
#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc
/* ADC channels for SPMI PMIC5 */
#define ADC5_REF_GND 0x00
#define ADC5_1P25VREF 0x01
#define ADC5_VREF_VADC 0x02
#define ADC5_VREF_VADC5_DIV_3 0x82
#define ADC5_VPH_PWR 0x83
#define ADC5_VBAT_SNS 0x84
#define ADC5_VCOIN 0x85
#define ADC5_DIE_TEMP 0x06
#define ADC5_USB_IN_I 0x07
#define ADC5_USB_IN_V_16 0x08
#define ADC5_CHG_TEMP 0x09
#define ADC5_BAT_THERM 0x0a
#define ADC5_BAT_ID 0x0b
#define ADC5_XO_THERM 0x0c
#define ADC5_AMUX_THM1 0x0d
#define ADC5_AMUX_THM2 0x0e
#define ADC5_AMUX_THM3 0x0f
#define ADC5_AMUX_THM4 0x10
#define ADC5_AMUX_THM5 0x11
#define ADC5_GPIO1 0x12
#define ADC5_GPIO2 0x13
#define ADC5_GPIO3 0x14
#define ADC5_GPIO4 0x15
#define ADC5_GPIO5 0x16
#define ADC5_GPIO6 0x17
#define ADC5_GPIO7 0x18
#define ADC5_SBUx 0x99
#define ADC5_MID_CHG_DIV6 0x1e
#define ADC5_OFF 0xff
/* 30k pull-up1 */
#define ADC5_BAT_THERM_30K_PU 0x2a
#define ADC5_BAT_ID_30K_PU 0x2b
#define ADC5_XO_THERM_30K_PU 0x2c
#define ADC5_AMUX_THM1_30K_PU 0x2d
#define ADC5_AMUX_THM2_30K_PU 0x2e
#define ADC5_AMUX_THM3_30K_PU 0x2f
#define ADC5_AMUX_THM4_30K_PU 0x30
#define ADC5_AMUX_THM5_30K_PU 0x31
#define ADC5_GPIO1_30K_PU 0x32
#define ADC5_GPIO2_30K_PU 0x33
#define ADC5_GPIO3_30K_PU 0x34
#define ADC5_GPIO4_30K_PU 0x35
#define ADC5_GPIO5_30K_PU 0x36
#define ADC5_GPIO6_30K_PU 0x37
#define ADC5_GPIO7_30K_PU 0x38
#define ADC5_SBUx_30K_PU 0x39
/* 100k pull-up2 */
#define ADC5_BAT_THERM_100K_PU 0x4a
#define ADC5_BAT_ID_100K_PU 0x4b
#define ADC5_XO_THERM_100K_PU 0x4c
#define ADC5_AMUX_THM1_100K_PU 0x4d
#define ADC5_AMUX_THM2_100K_PU 0x4e
#define ADC5_AMUX_THM3_100K_PU 0x4f
#define ADC5_AMUX_THM4_100K_PU 0x50
#define ADC5_AMUX_THM5_100K_PU 0x51
#define ADC5_GPIO1_100K_PU 0x52
#define ADC5_GPIO2_100K_PU 0x53
#define ADC5_GPIO3_100K_PU 0x54
#define ADC5_GPIO4_100K_PU 0x55
#define ADC5_GPIO5_100K_PU 0x56
#define ADC5_GPIO6_100K_PU 0x57
#define ADC5_GPIO7_100K_PU 0x58
#define ADC5_SBUx_100K_PU 0x59
/* 400k pull-up3 */
#define ADC5_BAT_THERM_400K_PU 0x6a
#define ADC5_BAT_ID_400K_PU 0x6b
#define ADC5_XO_THERM_400K_PU 0x6c
#define ADC5_AMUX_THM1_400K_PU 0x6d
#define ADC5_AMUX_THM2_400K_PU 0x6e
#define ADC5_AMUX_THM3_400K_PU 0x6f
#define ADC5_AMUX_THM4_400K_PU 0x70
#define ADC5_AMUX_THM5_400K_PU 0x71
#define ADC5_GPIO1_400K_PU 0x72
#define ADC5_GPIO2_400K_PU 0x73
#define ADC5_GPIO3_400K_PU 0x74
#define ADC5_GPIO4_400K_PU 0x75
#define ADC5_GPIO5_400K_PU 0x76
#define ADC5_GPIO6_400K_PU 0x77
#define ADC5_GPIO7_400K_PU 0x78
#define ADC5_SBUx_400K_PU 0x79
/* 1/3 Divider */
#define ADC5_GPIO1_DIV3 0x92
#define ADC5_GPIO2_DIV3 0x93
#define ADC5_GPIO3_DIV3 0x94
#define ADC5_GPIO4_DIV3 0x95
#define ADC5_GPIO5_DIV3 0x96
#define ADC5_GPIO6_DIV3 0x97
#define ADC5_GPIO7_DIV3 0x98
#define ADC5_SBUx_DIV3 0x99
/* Current and combined current/voltage channels */
#define ADC5_INT_EXT_ISENSE 0xa1
#define ADC5_PARALLEL_ISENSE 0xa5
#define ADC5_CUR_REPLICA_VDS 0xa7
#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9
#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab
#define ADC5_EXT_SENS_OFFSET 0xad
#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0
#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1
#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2
#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3
#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4
#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5
#define ADC5_MAX_CHANNEL 0xc0
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */

2
include/dt-bindings/interrupt-controller/arm-gic.h
View File

@@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* This header provides constants for the ARM GIC.
*/

2
include/dt-bindings/interrupt-controller/irq.h
View File

@@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* This header provides constants for most IRQ bindings.
*

17
include/dt-bindings/mfd/at91-usart.h Normal file
View File

@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides macros for AT91 USART DT bindings.
*
* Copyright (C) 2018 Microchip Technology
*
* Author: Radu Pirea <radu.pirea@microchip.com>
*
*/
#ifndef __DT_BINDINGS_AT91_USART_H__
#define __DT_BINDINGS_AT91_USART_H__
#define AT91_USART_MODE_SERIAL 0
#define AT91_USART_MODE_SPI 1
#endif /* __DT_BINDINGS_AT91_USART_H__ */

2
include/dt-bindings/net/mscc-phy-vsc8531.h
View File

@@ -18,9 +18,11 @@
#define VSC8531_LINK_100_1000_ACTIVITY 4
#define VSC8531_LINK_10_1000_ACTIVITY 5
#define VSC8531_LINK_10_100_ACTIVITY 6
#define VSC8584_LINK_100FX_1000X_ACTIVITY 7
#define VSC8531_DUPLEX_COLLISION 8
#define VSC8531_COLLISION 9
#define VSC8531_ACTIVITY 10
#define VSC8584_100FX_1000X_ACTIVITY 11
#define VSC8531_AUTONEG_FAULT 12
#define VSC8531_SERIAL_MODE 13
#define VSC8531_FORCE_LED_OFF 14

Some files were not shown because too many files have changed in this diff Show More